Download
Share
Print this page
  1. Manuals
  2. Brands
  3. Xilinx Manuals
  4. Controller
  5. XC4000 Series
  6. Manual

Xilinx XC4000 Series Manual

Field programmable gate arrays
Hide thumbs

Advertisement

Quick Links

Download this manual
®
September 18, 1996 (Version 1.04)
XC4000-Series Features
Note: XC4000-Series devices described in this data sheet
include
the
XC4000E,
XC4000XL. This information does not apply to the older
Xilinx families: XC4000, XC4000A, XC4000D or XC4000H.
For information on these devices, see the Xilinx W
at http://www.xilinx.com.
• Third Generation Field-Programmable Gate Arrays
- Select-RAM
TM
memory: on-chip ultra-fast RAM with
- synchronous write option
- dual-port RAM option
- Fully PCI compliant (speed grades -3 and faster)
- Abundant flip-flops
- Flexible function generators
- Dedicated high-speed carry logic
- Wide edge decoders on each edge
- Hierarchy of interconnect lines
- Internal 3-state bus capability
- 8 global low-skew clock or signal distribution
networks
• System Performance to 66 MHz
• Flexible Array Architecture
• Systems-Oriented Features
- IEEE 1149.1-compatible boundary scan logic
support
- Individually programmable output slew rate
- Programmable input pull-up or pull-down resistors
- 12-mA sink current per XC4000E output (4 mA per
XC4000L output)
• Configured by Loading Binary File
- Unlimited reprogrammability
• Readback Capability
• Backward Compatible with XC4000 Devices
• XACT step Development System runs on '386/'486/
Pentium-type PC, Sun-4, and Hewlett-Packard 700
series
- Interfaces to popular design environments
- Fully automatic mapping, placement and routing
- Interactive design editor for design optimization
- RAM/ROM compiler
Low-Voltage Versions Available
• Low-Voltage Devices Function at 3.0 - 3.6 Volts
• XC4000L: Low-Voltage Versions of XC4000E devices
• XC4000XL: Low-Voltage Versions of XC4000EX
devices
September 18, 1996 (Version 1.04)
XC4000EX,
XC4000L,
and
LINX
EB
XC4000 Series
Field Programmable Gate Arrays
Product Specification
Additional XC4000EX/XL Features
• Highest Capacity — Over 130,000 Usable Gates
• Additional Routing Over XC4000E
- almost twice the routing capacity for high-density
designs
• Buffered Interconnect for Maximum Speed
• New Latch Capability in Configurable Logic Blocks
• Improved VersaRing
TM
I/O Interconnect for Better Fixed
Pinout Flexibility
• Flexible New High-Speed Clock Network
- 8 additional Early Buffers for shorter clock delays
- 4 additional FastCLK
- Virtually unlimited number of clock signals
• Optional Multiplexer or 2-input Function Generator on
Device Outputs
• High-Speed Parallel Express
• Improved I/O Setup and Clock-to-Output with FastCLK
and Global Early Buffers
• 4 Additional Address Bits in Master Parallel
Configuration Mode
Introduction
XC4000-Series high-performance, high-capacity Field Pro-
grammable Gate Arrays (FPGAs) provide the benefits of
custom CMOS VLSI, while avoiding the initial cost, long
development cycle, and inherent risk of a conventional
masked gate array.
The result of eleven years of FPGA design experience and
feedback from thousands of customers, these FPGAs com-
bine architectural versatility, on-chip Select-RAM memory
with edge-triggered and dual-port modes, increased speed,
abundant routing resources, and new, sophisticated soft-
ware to achieve fully automated implementation of com-
plex, high-density, high-performance designs.
The XC4000 Series currently has 19 members, as shown
in
Table
1.
TM
buffers for fastest clock input
TM
Configuration Mode
4-5

Advertisement

loading

Related Manuals for Xilinx XC4000 Series

Summary of Contents for Xilinx XC4000 Series

  • Page 1 • XACT step Development System runs on '386/'486/ plex, high-density, high-performance designs. Pentium-type PC, Sun-4, and Hewlett-Packard 700 The XC4000 Series currently has 19 members, as shown series Table - Interfaces to popular design environments...
  • Page 2 Input/Output Blocks (IOBs). They have high-volume unit cost, a design can first be implemented in generous routing resources to accommodate the most the XC4000E or XC4000EX, then migrated to one of Xilinx’ complex interconnect patterns. compatible HardWire mask-programmed devices.
  • Page 3 Table 2: Density and Performance for Several Common Circuit Functions in XC4000E Design Class Function CLBs Used XC4000E-3 XC4000E-2 Units 256 x 8 Single Port (read/modify/write) 32 x 16 bit FIFO Memory simultaneous read/write MUXed read/write 9 bit Shift Register (with enable) 16 bit Pre-Scaled Counter 16 bit Loadable Counter 16 bit Accumulator...
  • Page 4 Vcc. Also, the configurable pull- PCI Compliance up resistor in the XC4000 Series is a p-channel transistor XC4000-Series -3 and faster speed grades are fully PCI that pulls to Vcc, whereas in the XC4000 it is an n-channel compliant.
  • Page 5 Global Signal Access to Logic Faster Input and Output There is additional access from global clocks to the F and G A fast, dedicated early clock sourced by global clock buffers function generator inputs. is available for the IOBs. To ensure synchronization with the regular global clocks, a Fast Capture latch driven by the Configuration Pin Pull-Up Resistors early clock is available.
  • Page 6 XC4000 Series Field Programmable Gate Arrays Table 3: CLB Count of Selected XC4000-Series Soft Macros 7400 Equivalents CLBs Barrel Shifters CLBs Multiplexers CLBs ‘138 brlshft4 m2-1e ‘139 brlshft8 m4-1e ‘147 m8-1e 4-Bit Counters ‘148 m16-1e ‘150 cd4cd Registers ‘151 cd4cle rd4r ‘152...

  • Page 7: Detailed Functional Description

    66 MHz and internal performance in Each CLB contains two storage elements that can be used excess of 150 MHz. Compared to older Xilinx FPGA fami- to store the function generator outputs. However, the stor- lies, XC4000-Series devices are more powerful.
  • Page 8 XC4000 Series Field Programmable Gate Arrays C 1 • • • C 4 D IN /H 2 SR/H 0 Bypass CONTROL LOGIC FUNCTION G1-G4 LOGIC FUNCTION F', G', Bypass CONTROL LOGIC FUNCTION F1-F4 (CLOCK) Multiplexer Controlled by Configuration Program X6692 Figure 1: Simplified Block Diagram of XC4000-Series CLB (RAM and Carry Logic functions not shown)
  • Page 9 Each flip-flop is configured as either globally set or reset in the same way that the local set/reset (SR) is specified. The abundance of flip-flops in the XC4000 Series invites Therefore, if a flip-flop is set by SR, it is also set by GSR.
  • Page 10 RAM. supported. Three application notes are available from Xilinx that dis- RAM configuration options are selected by placing the cuss edge-triggered RAM: “ XC4000E Edge-Triggered and appropriate library symbol.
  • Page 11 C 1 • • • C 4 D IN WRITE 16-LATCH DECODER ARRAY G 1 • • • G 4 1 of 16 LATCH ENABLE READ ADDRESS WRITE PULSE D IN WRITE 16-LATCH DECODER ARRAY F 1 • • • F 4 1 of 16 LATCH ENABLE...
  • Page 12 XC4000 Series Field Programmable Gate Arrays RAM Inputs and Outputs The F1-F4 and G1-G4 inputs to the function generators act WCLK (K) as address lines, selecting a particular memory cell in each look-up table. The functionality of the CLB control signals changes when the function generators are configured as RAM.
  • Page 13 Dual-Port Edge-Triggered Mode Therefore, by using A[3:0] for the write address and DPRA[3:0] for the read address, and reading only the DPO In dual-port mode, both the F and G function generators output, a FIFO that can read and write simultaneously is are used to create a single 16x1 RAM array with one write easily generated.
  • Page 14 XC4000 Series Field Programmable Gate Arrays C 1 • • • C 4 WRITE 16-LATCH DECODER ARRAY 1 of 16 LATCH ENABLE READ WRITE PULSE ADDRESS G 1 • • • G 4 WRITE 16-LATCH DECODER ARRAY F 1 • • • F 4...
  • Page 15 Address before the next rising edge of the system clock. Several G1-G4 older application notes are available from Xilinx that dis- cuss the design of level-sensitive RAMs. These application Write Enable notes include XAPP031, “ Using the XC4000 RAM Capabil- F’...
  • Page 16 XC4000 Series Field Programmable Gate Arrays C 1 • • • C 4 D IN Enable WRITE 16-LATCH DECODER ARRAY G 1 • • • G 4 1 of 16 READ ADDRESS D IN Enable WRITE 16-LATCH DECODER ARRAY F 1 • • • F 4...
  • Page 17 Fast Carry Logic The dedicated carry logic is discussed in detail in Xilinx document XAPP 013: “ Using the Dedicated Carry Logic in Each CLB F and G function generator contains dedicated XC4000 .” This discussion also applies to XC4000E...
  • Page 18 XC4000 Series Field Programmable Gate Arrays DOWN CARRY LOGIC CARRY C OUT0 CARRY X6699 Figure 13: Fast Carry Logic in XC4000E CLB (shaded area not present in XC4000EX) 4-22 September 18, 1996 (Version 1.04)
  • Page 19 OUT0 FUNCTION GENERATORS IN UP X2000 IN DOWN Figure 14: Detail of XC4000E Dedicated Carry Logic C OUT C OUT0 FUNCTION GENERATORS C IN UP X6701 Figure 15: Detail of XC4000EX Dedicated Carry Logic (shaded areas show differences from XC4000E carry logic) September 18, 1996 (Version 1.04) 4-23...
  • Page 20 XC4000 Series Field Programmable Gate Arrays Input/Output Blocks (IOBs) Table 10: Supported Sources for XC4000-Series Device Inputs User-configurable input/output blocks (IOBs) provide the interface between external package pins and the internal XC4000-Series Inputs logic. Each IOB controls one package pin and can be con- 3.3 V,...
  • Page 21 Passive Slew Rate Pull-Up/ Control Pull-Down Flip-Flop Output Buffer Output Clock Flip- Input Buffer Flop/ Latch Delay Clock Enable Input Clock X6704 Figure 16: Simplified Block Diagram of XC4000E IOB Passive Slew Rate Pull-Up/ Control Pull-Down Output MUX Flip-Flop Output Buffer Output Clock Input...
  • Page 22 XC4000 Series Field Programmable Gate Arrays Optional Delay Guarantees Zero Hold Time Additional Input Latch for Fast Capture (XC4000EX only) The data input to the register can optionally be delayed by several nanoseconds. With the delay enabled, the setup The XC4000EX IOB has an additional optional latch on the time of the input flip-flop is increased so that normal clock...
  • Page 23 By default, the output pull-up structure is configured as a input. By default, if the Fast Capture latch is used, the Xilinx TTL-like totem-pole. The High driver is an n-channel pull- software assumes a Global Early buffer is driving the clock, up transistor, pulling to a voltage one transistor threshold and selects MEDDELAY to ensure a zero hold time.
  • Page 24 Therefore, are turned on simultaneously at the end of configuration. the Xilinx software does not move logic into the IOB func- When the configuration process is finished and the device tion generators unless explicitly directed to do so.
  • Page 25 are independent, except that in the XC4000EX, the Fast OMUX2 Capture latch shares an IOB input with the output clock pin. Early Clock for IOBs (XC4000EX only) Special early clocks are available for IOBs. These clocks OAND2 X6598 are sourced by the same sources as the Global Low-Skew X6599 buffers, but are separately buffered.
  • Page 26 XC4000 Series Field Programmable Gate Arrays The buffer enable is an active-High 3-state (i.e. an active- WAND4, WAND8, and WAND16 are also available. See Low enable), as shown in Table the XACT Libraries Guide for further information. Another 3-state buffer with similar access is located near The T pin is internally tied to the I pin.
  • Page 27 Wide Edge Decoders INTERCONNECT Dedicated decoder circuitry boosts the performance of wide decoding functions. When the address or data field is wider than the function generator inputs, FPGAs need multi-level decoding and are thus slower than PALs. XC4000-Series CLBs have nine inputs. Any decoder of up to nine inputs is, therefore, compact and fast.
  • Page 28 XC4000 Series Field Programmable Gate Arrays Programmable Interconnect CLB Routing Connections A high-level diagram of the routing resources associated All internal connections are composed of metal segments with one CLB is shown in Figure 26. The shaded arrows with programmable switching points and switching matrices represent routing present only in XC4000EX devices.
  • Page 29 Quad Single Double Long Direct Connect Long Quad Long Global Long Double Single Global Carry Direct Clock Clock Chain Connect x5994 Figure 26: High-Level Routing Diagram of XC4000-Series CLB (shaded arrows indicate XC4000EX only) September 18, 1996 (Version 1.04) 4-33...
  • Page 30 XC4000 Series Field Programmable Gate Arrays QUAD DOUBLE SINGLE DOUBLE LONG F4 C4 G4 DIRECT FEEDBACK F2 C2 G2 LONG Common to XC4000E and XC4000EX XC4000EX only Programmable Switch Matrix Figure 27: Detail of Programmable Interconnect Associated with XC4000-Series CLB 4-34 September 18, 1996 (Version 1.04)
  • Page 31 Single-Length Lines Single-length lines provide the greatest interconnect flexi- bility and offer fast routing between adjacent blocks. There are eight vertical and eight horizontal single-length lines associated with each CLB. These lines connect the switch- Double ing matrices that are located in every row and a column of CLBs.
  • Page 32 XC4000 Series Field Programmable Gate Arrays Quad Lines (XC4000EX only) Each buffered switch matrix contains one buffer and six pass transistors. It resembles the programmable switch XC4000EX devices also include twelve vertical and twelve matrix shown in Figure 28, with the addition of a program- horizontal quad lines per CLB row and column.
  • Page 33 Longlines Direct Interconnect (XC4000EX only) Longlines form a grid of metal interconnect segments that The XC4000EX offers two direct, efficient and fast connec- run the entire length or width of the array. Longlines are tions between adjacent CLBs. These nets facilitate a data intended for high fan-out, time-critical signal nets, or nets flow from the left to the right side of the device, or from the that are distributed over long distances.
  • Page 34 XC4000 Series Field Programmable Gate Arrays I/O Routing Figure 33 is a detailed diagram of the XC4000E and XC4000EX VersaRing. The area shown includes two IOBs. XC4000-Series devices have additional routing around the There are two IOBs per CLB row or column, therefore this IOB ring.
  • Page 35 QUAD DOUBLE SINGLE DOUBLE LONG DIRECT LONG Common to XC4000E and XC4000EX XC4000EX only Figure 33: Detail of Programmable Interconnect Associated with XC4000-Series IOB (Left Edge) September 18, 1996 (Version 1.04) 4-39...
  • Page 36 XC4000 Series Field Programmable Gate Arrays Octal I/O Routing (XC4000EX only) most recently buffered before the turn has the farthest dis- tance to travel before the next buffer, as shown in Between the XC4000EX CLB array and the pad ring, eight...
  • Page 37 Global Nets and Buffers Four Primary Global buffers offer the shortest delay and negligible skew. Four Secondary Global buffers have Both the XC4000E and the XC4000EX have dedicated glo- slightly longer delay and slightly more skew due to poten- bal networks. These networks are designed to distribute tially heavier loading, but offer greater flexibility when used clocks and other high fanout control signals throughout the to drive non-clock CLB inputs.
  • Page 38 XC4000 Series Field Programmable Gate Arrays BUFGS BUFGP PGCK1 SGCK4 PGCK4 SGCK1 BUFGS BUFGP locals locals locals locals Any BUFGS Any BUFGS locals locals One BUFGP One BUFGP per Global Line per Global Line locals locals BUFGS BUFGP SGCK3 PGCK2...
  • Page 39 Global Nets and Buffers (XC4000EX only) Early and Global Low-Skew buffers share a common input; they cannot be driven by two different signals. Eight vertical longlines in each CLB column are driven by special global buffers. These longlines are in addition to Choosing an XC4000EX Clock Buffer the vertical longlines used for standard interconnect.
  • Page 40 XC4000 Series Field Programmable Gate Arrays X6751 X6753 Figure 38: Left and Right BUFGEs Can Drive Any or Figure 37: Any BUFGLS (GCK1 - GCK8) Can All Clock Inputs in Same Quadrant or Edge (GCK1 is Drive Any or All Clock Inputs on the Device shown.
  • Page 41 The Global Early buffers can be driven by either semi-ded- icated pads or internal logic. They share pads with the Glo- bal Low-Skew buffers, so a single net can drive both global buffers, as described above. To use a Global Early buffer, place a BUFGE element in a schematic or in HDL code.

  • Page 42: Power Distribution

    XC4000 Series Field Programmable Gate Arrays Power Distribution Pin Descriptions Power for the FPGA is distributed through a grid to achieve There are three types of pins in the XC4000-Series high noise immunity and isolation between logic and I/O. devices: Inside the FPGA, a dedicated Vcc and Ground ring sur- •...
  • Page 43 Table 18: Pin Descriptions During After Pin Name Config. Config. Pin Description Permanently Dedicated Pins Eight or more (depending on package) connections to the nominal +5 V supply voltage (+3.3 V for low-voltage devices). All must be connected, and each must be decoupled with a 0.01 - 0.1 µF capacitor to Ground.
  • Page 44 XC4000 Series Field Programmable Gate Arrays Table 18: Pin Descriptions (Continued) During After Pin Name Config. Config. Pin Description If boundary scan is used, this pin is the Test Data Output. If boundary scan is not used, this pin is a 3-state output without a register, after configuration is completed.
  • Page 45 Table 18: Pin Descriptions (Continued) During After Pin Name Config. Config. Pin Description These four inputs are used in Asynchronous Peripheral mode. The chip is selected when CS0 is Low and CS1 is High. While the chip is selected, a Low on Write Strobe (WS) loads the data present on the D0 - D7 inputs into the internal data buffer.

  • Page 46: Boundary Scan

    The functional shown in Table details can be found in the IEEE 1149.1 specification and Table 19: Boundary Scan Instructions are also discussed in the Xilinx application note XAPP 017: " Boundary Scan in XC4000 Devices ." Instruction Test I/O Data...
  • Page 47 EXTEST SLEW PULL PULL TS INV RATE DOWN TS/OE 3-State TS TS - capture Boundary Scan TS - update OUTPUT INVERT OUTPUT Ouput Data O INVERT Ouput Clock OK O - capture Clock Enable Boundary Q - capture Scan O - update I - capture Boundary Scan...
  • Page 48 XC4000 Series Field Programmable Gate Arrays DATA IN IOB.Q IOB.T IOB.I IOB.Q BYPASS REGISTER IOB.T INSTRUCTION REGISTER INSTRUCTION REGISTER BYPASS REGISTER IOB.I IOB.O DATAOUT UPDATE EXTEST SHIFT/ CLOCK DATA CAPTURE REGISTER X1523 Figure 43: XC4000-Series Boundary Scan Logic 4-52 September 18, 1996 (Version 1.04)
  • Page 49 Figure ing configuration. In some applications, a situation may The device-specific pinout tables for the XC4000 Series occur where TMS or TCK is driven during configuration. include the boundary scan locations for each IOB pin.

  • Page 50: Product Availability

    Table 25 Table 27 show the planned packages and speed grades for XC4000-Series devices. Call your local sales office for the latest availability information, or see the Xilinx W LINX at http://www.xilinx.com for the latest revision of the specifications. Table 25: Component Availability Chart for XC4000E FPGAs...
  • Page 51 XC4000 Series Field Programmable Gate Arrays Table 26: Component Availability Chart for XC4000EX FPGAs Speed HQ208 HQ240 PG299 HQ304 BG352 PG411 BG432 Grade XC4028EX XC4036EX XC4044EX C = Commercial, T = 0° to +85° C I = Industrial, T = -40° to +100° C M = Mil Temp, T = -55°...
  • Page 52 All pinouts defined at the time of publication are included in these tables. Additional information may be available. Call your local sales office or see the Xilinx W LINX at http://www.xilinx.com for the latest information.
  • Page 53 XC4000 Series Field Programmable Gate Arrays Table 29: Maximum User I/O for XC4000EX Device/Package Combinations No. of Pins Package (Code) XC4028EX XC4036EX XC4044EX Maximum User I/O HQFP (HQ) HQFP (HQ) PGA (PG) HQFP (HQ) BGA (BG) PGA (PG) BGA (BG) Note: This table includes standard user-programmable I/O.

  • Page 54: Ordering Information

    Ordering Information Example: XC4013E-3HQ240C Device Type Temperature Range C = Commercial (T = 0 to +85°C) Speed Grade I = Industrial (T = -40 to +100°C) M = Military (T = -55 to+125°C) Number of Pins Package Type PC = Plastic Lead Chip Carrier BG = Ball Grid Array PQ = Plastic Quad Flat Pack PG = Ceramic Pin Grid Array...
  • Page 55 Xilinx assumes no obligation to correct any errors contained herein or to Xilinx does not assume any liability arising out of the appli- advise any user of this text of any correction if such be cation or use of any product described or shown herein;...

This manual is also suitable for:

Xc4003eXc4005eXc4005lXc4006eXc4008eXc4010e ... Show all