Xilinx Zynq-7000 Design Manual page 64

For PS_DDR_DQxx, ensure that byte lines are kept together. PS_DDR_ADDR0 should always be
Note:
used. If bits must be omitted for chip select or other functionality, omit upper bit (PS_ADDR14)
instead.
X-Ref Target - Figure 5-8
In a balanced T-branch configuration, trace lengths TL1, TL2 and Tsub shall be kept as short
as possible; Rterm shall be close to and balanced among the loads.
In a point-to-point configuration, Rterm shall be placed behind and close to the last load.
In the fly-by topology, TL0 should be kept from 0-64 mm, with TL1 14 mm ±0.1 mm, and
TL2 from 6-20 mm.
Table 5-12 shows the recommended routing topologies. Byte and bit swapping is allowed
to facilitate PCB routing, except for LPDDR2, which specifically forbids swapping. When
swapping bits, keep all bits within the same byte group.
Table 5-12: DDR Routing Topology
Signal Group
Data
Clock
Address,
Command,
Control
Zynq-7000 PCB Design Guide
UG933 (v1.8) November 7, 2014
VTT
Rterm
ZYNQ
DDR
Tsub
Point-to-point
TL0 TL1 TL1
DDR DDR DDR
Fly-by
Figure 5-8: DDR Routing Topologies
LPDDR2
Point-to-point Point-to-point
Point-to-point Point-to-point
T-branch T-branch
N/A T-branch
Point-to-point Point-to-point
T-branch T-branch
N/A T-branch
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Chapter 5: Processing System (PS) Power and Signaling
TL2
DDR
TL1
VTT
DDR
Rterm
TL0 Tsub
DDR
DDR
Balanced T-branch
VTT
Rterm
TL2
TL1
DDR
UG585_c30_07_091913
DDR2 DDR3/3L
Point-to-point
Point-to-point
Fly-by
Fly-by
Point-to-point
Fly-by/T-branch
Fly-by/T-branch
Number of DDR
Devices
1
2
4
1
2
4
64
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