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Xilinx LogiCORE IP Product Manual

Xilinx LogiCORE IP Product Manual

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XAUI v12.3
LogiCORE IP Product Guide
Vivado Design Suite
PG053 April 6, 2016

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Summary of Contents for Xilinx LogiCORE IP

  • Page 1 XAUI v12.3 LogiCORE IP Product Guide Vivado Design Suite PG053 April 6, 2016...

  • Page 2: Table Of Contents

    Debug Port ..............89 XAUI v12.3 Product Guide www.xilinx.com Send Feedback...
  • Page 3 Finding Help on xilinx.com ........

  • Page 4: Send Feedback

    Please Read: Important Legal Notices ..........142 XAUI v12.3 Product Guide www.xilinx.com Send Feedback...

  • Page 5: Ip Facts

    Designed to 10-Gigabit Ethernet IEEE Design Entry Vivado® Design Suite 802.3-2012 specification Simulation For supported simulators, see the Xilinx Design Tools: Release Notes Guide. • Supports 20G double-rate XAUI (Double Synthesis Vivado Synthesis XAUI) using four transceivers at 6.25 Gb/s.

  • Page 6: Chapter 1: Overview

    Optional MDIO Interface is a two-wire low-speed serial interface used to manage the core. • Four Device-Specific Transceivers (integrated in the FPGAs) provide the high-speed transceivers as well as 8B/10B encode and decode and elastic buffering in the receive datapath. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 7 Lane 2 Synchronization Transceiver Lane 3 mdio Management Reference Clocks and clock Reset Logic clk156_out Reset X13667 Figure 1‐1: Architecture of the XAUI IP Core with Client-Side User Logic XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...

  • Page 8: Additional Features

    For best results, previous experience building high performance, pipelined Field Programmable Gate Array (FPGA) designs using Xilinx implementation software and Xilinx Design Constraints (XDC) is recommended. Contact your local Xilinx representative for a closer review and estimation for your specific requirements. XAUI v12.3 Product Guide www.xilinx.com...

  • Page 9: Applications

    After its publication, the applications of XAUI have extended beyond 10-Gigabit Ethernet to the backplane and other general high-speed interconnect applications. Figure 1-3 shows a typical backplane and other general high-speed interconnect applications. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...

  • Page 10: Licensing And Ordering Information

    Figure 1‐3: Typical Backplane Application for XAUI Licensing and Ordering Information This Xilinx LogiCORE™ IP module is provided at no additional cost with the Xilinx Vivado® Design Suite under the terms of the Xilinx End User License. Information about this and...

  • Page 11: Feedback

    Xilinx welcomes comments and suggestions about the XAUI core and the documentation supplied with the core. Core For comments or suggestions about the XAUI core, submit a webcase from Xilinx Support web page. Be sure to include the following information: •...

  • Page 12: Chapter 2: Product Specification

    XGMII interface, the latency through the core in the receive direction is equal to 4 5 clock cycles of usrclk. – XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...

  • Page 13: Resource Utilization

    UltraScale™ architecture. Table 2‐2: Device Utilization – UltraScale Architectures Shared Logic MDIO Management LUTs In Example Design FALSE In Example Design TRUE 1094 In Core FALSE In Core TRUE 1094 XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 14 Table 2‐5: Device Utilization – Artix-7 FPGAs Shared Logic MDIO Management LUTs In Example Design FALSE 1027 1186 In Example Design TRUE 1144 1285 In Core FALSE 1107 1186 In Core TRUE 1223 1285 XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...

  • Page 15: Verification

    Clock compensation • Recovery from error conditions Hardware Verification The core has been used in several hardware test platforms within Xilinx. In particular, the ® core has been used in a test platform design with the Xilinx 10-Gigabit Ethernet MAC. This design comprises the MAC, XAUI, a ping loopback First In First Out (FIFO), and a test pattern generator all under embedded processor control.

  • Page 16: Port Descriptions

    Async receiving illumination and is therefore not just putting out noise. If an optical module is not in use, this four-wire bus should be tied to 1111. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 17 Starts the TX PMA reset process. gt0_txpcsreset_in Async Starts the TX PCS reset process. When asserted the serial transceiver TX has finished gt0_txresetdone_out clk156_out reset and is ready for use. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 18 The txpolarity port can invert the polarity of outgoing gt0_txpolarity_in clk156_out data. GT0 RX Decision Feedback Equalizer (DFE) (GTXE2 and GTHE2) RX datapath. gt0_rxlpmen_in Async 0: DFE. 1: LPM. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 19 (GTHE2) Digital Monitor Output Bus gt0_dmonitorout_out[14:0] Async (GTPE2) Digital Monitor Output Bus GT0 Status Active-High indicates the corresponding byte of the gt0_rxdisperr_out[3:0] clk156_out received data has a disparity error XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 20 When asserted the serial transceiver RX has finished gt1_rxresetdone_out clk156_out reset and is ready for use. GT1 Clocking gt1_rxbufstatus_out[2:0] clk156_out RX buffer status. gt1_txphaligndone_out Async TX phase alignment done. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 21 (GTPE2) Determines whether the value of the gt1_rxlpmlfhold_in Async low-frequency boost is either held or adapted. (GTPE2) Determines whether the low-frequency boost gt1_rxlpmlfovrden_in Async is controlled by an attribute or a signal. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 22 0: No read or write operation performed. 1: enables a read or write operation. Data bus for writing configuration data to the gt2_drpdi[15:0] dclk transceiver for channel 2. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 23 This port is driven High and then deasserted to start gt2_eyescanreset_in Async the EYESCAN reset process. Asserts High for one rec_clk cycle when an (unmasked) gt2_eyescandataerror_out Async error occurs while in the COUNT or ARMED state. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 24 GT2 PRBS gt2_rxprbscntreset_in clk156_out Resets the PRBS error counter. This non-sticky status output indicates that PRBS gt2_rxprbserr_out clk156_out errors have occurred. gt2_rxprbssel_in[2:0] clk156_out Receiver PRBS checker test pattern control. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 25 (GTPE2 all configurations or GTHE2 10G configuration). Indicates the DRP interface is being gt3_drp_busy dclk used internally by the serial transceiver and should not be driven until this signal is deasserted. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 26 Determines the loopback mode. GT3 Polarity The rxpolarity port can invert the polarity of incoming gt3_rxpolarity_in clk156_out data. The txpolarity port can invert the polarity of outgoing gt3_txpolarity_in clk156_out data. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 27 Hold the CDR control loop frozen. GT3 Digital Monitor gt3_dmonitorout_out[7:0] Async (GTXE2) Digital Monitor Output Bus gt3_dmonitorout_out[14:0] Async (GTHE2) Digital Monitor Output Bus gt3_dmonitorout_out[14:0] Async (GTPE2) Digital Monitor Output Bus XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 28 Data bus for reading configuration data from the gt1_drpdo[15:0] dclk transceiver for channel 1. Indicates operation is complete for write operations and gt1_drprdy dclk data is valid for read operations for channel 1. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 29 GT lanes 0, 1, 2 and 3 respectively. See the appropriate transceiver user guide for more details. TX Reset and Initialization gt_txpmareset[3:0] Async Starts the TX PMA reset process. gt_txpcsreset[3:0] Async Starts the TX PCS reset process. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 30 RX Decision Feedback Equalizer (DFE) RX datapath. gt_rxlpmen[3:0] Async 0: DFE. 1: LPM. gt_rxdfelpmreset[3:0] Async Reset for LPM and DFE datapath. TX Driver gt_txpostcursor[19:0] Async Transmitter post-cursor TX post-emphasis control. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 31 Chapter 5, Interfacing to the Core. Table 2‐10: MDIO Management Interface Ports Clock Signal Name Direction Description Domain Async Management clock mdio_in Async MDIO input XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 32 Included in the example design top-level sources are circuits for clock and reset management. These can include Digital Clock Managers (DCMs), Mixed-Mode Clock Managers (MMCMs), reset synchronizers, or other useful utility circuits that might be useful in your particular application. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 33 This active-High PLL frequency lock signal indicates that the PLL clk156_lock frequency is within predetermined tolerance. The transceiver and its clock outputs are not reliable until this condition is met. reset Asynchronous external reset XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...

  • Page 34: Register Space

    3.2, 3.3 PCS Device Identifier PCS Speed Ability 3.5, 3.6 PCS Devices in Package 10G PCS Control 2 10G PCS Status 2 3.9 to 3.13 Reserved 3.14, 3.15 Package Identifier XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 35 When set to 1, the serial transceivers are placed in down a low-power state. Set to 0 to return to normal operation The block always returns 0 for these bits and 1.0.10:7 Reserved All 0s ignores writes. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 36 The block always returns 1 for this bit. Status Power Down 1.1.1 The block always returns 1 for this bit. Ability 1.1.0 Reserved The block always returns 0 for this bit. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 37 MDIO Register 1.4: PMA/PMD Speed Ability Figure 2-4 shows the MDIO Register 1.4: PMA/PMD Speed Ability. X-Ref Target - Figure 2-4 Reg 1.4 X13685 Figure 2‐4: PMA/PMD Speed Ability Register XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 38 The block always returns 0 for this bit. Device 1 Present The block always returns 0 for these 1.6.13:0 Reserved All 0s bits. The block always returns 0 for these 1.5.15:6 Reserved All 0s bits. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 39 The block always returns 0 for these bits 1.7.15:3 Reserved All 0s and ignores writes. The block always returns 100 for these PMA/PMD Type 1.7.2:0 bits and ignores writes. This corresponds Selection to the 10GBASE-X PMA/PMD. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 40 The block always returns 0 for this 1.8.5 Ability bit. 10GBASE-LX4 The block always returns 1 for this 1.8.4 Ability bit. 10GBASE-SW The block always returns 0 for this 1.8.3 Ability bit. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 41 1 = Signal OK on receive Lane 1 PMD Receive 0 = Signal not OK on receive Lane 1 1.10.2 Signal OK 1 This is the value of the signal_detect[1] port. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 42 Value PMA/PMD The block always returns 0 for these 1.15.15:0 All 0s Package Identifier bits. PMA/PMD The block always returns 0 for these 1.14.15:0 All 0s Package Identifier bits. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 43 The block always returns 0s for these bits 3.0.5:2 All 0s Selection and ignores writes. The block always returns 0 for this bit and 3.0.1:0 Reserved All 0s ignores writes. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 44 Clears to current Link Status on read. Power Down 3.1.1 The block always returns 1 for this bit. Ability The block always returns 0 for this bit and 3.1.0 Reserved ignores writes. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 45 MDIO Register 3.4: PCS Speed Ability Figure 2-13 shows the MDIO Register 3.4: PCS Speed Ability. X-Ref Target - Figure 2-13 Reg 3.4 X13694 Figure 2‐13: PCS Speed Ability Register XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 46 The block always returns 0 for this bit. Device 2 Present Vendor-specific 3.6.14 The block always returns 0 for this bit. Device 1 Present The block always returns 0 for these 3.6.13:0 Reserved All 0s bits. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 47 The block always returns 0 for these bits and 3.7.15:2 Reserved All 0s ignores writes. PCS Type The block always returns 01 for these bits and 3.7.1:0 Selection ignores writes. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 48 The block always returns 0 for this bit. Capable 10GBASE-X 3.8.1 The block always returns 1 for this bit. Capable 10GBASE-R 3.8.0 The block always returns 0 for this bit. Capable XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 49 MDIO Register 3.24: 10GBASE-X Status Figure 2-18 shows the MDIO Register 3.24: 10GBase-X Status. X-Ref Target - Figure 2-18 13 12 11 10 Reg 3.24 X13699 Figure 2‐18: 10GBASE-X Status Register XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 50 MDIO Register 3.25: 10GBASE-X Test Control Figure 2-19 shows the MDIO Register 3.25: 10GBase-X Test Control. X-Ref Target - Figure 2-19 Reg 3.25 X13700 Figure 2‐19: Test Control Register XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 51 0 = Transmit test pattern disabled 11 = Reserved 10 = Mixed frequency test pattern Test Pattern 3.25.1:0 Select 01 = Low frequency test pattern 00 = High frequency test pattern XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 52 MDIO Register 5.0: DTE XS Control 1. X-Ref Target - Figure 2-20 15 14 13 12 11 10 Reg 5.0 X13710 Figure 2‐20: DTE XS Control 1 Register XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 53 MDIO Register 5.1: DTE XS Status 1 Figure 2-21 shows the MDIO Register 5.1: DTE XS Status 1. X-Ref Target - Figure 2-21 Reg 5.1 X13711 Figure 2‐21: DTE XS Status 1 Register XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 54 Figure 2-22 shows the MDIO Registers 5.2 and 5.3: DTE XS Device Identifier. X-Ref Target - Figure 2-22 Reg 5.2 Reg 5.3 X13712 Figure 2‐22: DTE XS Device Identifier Registers XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 55 The block always returns 0 for these bits and 5.4.15:1 Reserved All 0s ignores writes. The block always returns 1 for this bit and 5.4.0 10G Capable ignores writes. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 56 The block always returns 0 for this bit. 5.5.1 PMA/PMD Present The block always returns 0 for this bit. Clause 22 Device 5.5.0 The block always returns 0 for this bit. Present XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 57 Fault 0 = No fault condition on receive path unless the fault is still present. 5.8.9:0 Reserved The block always returns 0 for these bits. All 0s XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 58 High frequency test pattern of “1010101010..” at each device-specific transceiver output • Low frequency test pattern of “111110000011111000001111100000..” at each device-specific transceiver output • mixed frequency test pattern of “111110101100000101001111101011000001010...” at each device-specific transceiver output. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 59 1 = Lane 1 is synchronized; 5.24.1 Lane 1 Sync 0 = Lane 1 is not synchronized. 1 = Lane 0 is synchronized; 5.24.0 Lane 0 Sync 0 = Lane 0 is not synchronized. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 60 0 = Transmit test pattern disabled 11 = Reserved 10 = Mixed frequency test pattern Test Pattern 5.25.1:0 Select 01 = Low frequency test pattern 00 = High frequency test pattern XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 61 MDIO Register 4.0: PHY XS Control 1. X-Ref Target - Figure 2-29 15 14 13 12 11 10 Reg 4.0 X13701 Figure 2‐29: PHY XS Control 1 Register XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 62 MDIO Register 4.1: PHY XS Status 1 Figure 2-30 shows the MDIO Register 4.1: PHY XS Status 1. X-Ref Target - Figure 2-30 Reg 4.1 X13702 Figure 2‐30: PHY XS Status 1 Register XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 63 Figure 2-31 shows the MDIO Registers 4.2 and 4.3: PHY XS Device Identifier. X-Ref Target - Figure 2-31 Reg 4.2 Reg 4.3 X13703 Figure 2‐31: PHY XS Device Identifier Registers XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 64 The block always returns 0 for these bits and 4.4.15:1 Reserved All 0s ignores writes. The block always returns 1 for this bit and 4.4.0 10G Capable ignores writes. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 65 The block always returns 0 for this bit. 4.5.1 PMA/PMD Present The block always returns 0 for this bit. Clause 22 device 4.5.0 The block always returns 0 for this bit. present XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 66 0 = No fault condition on receive path after a read unless the fault is still present. 4.8.9:0 Reserved The block always returns 0 for these bits. All 0s XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 67 MDIO Register 4.24: 10G XGXS Lane Status. X-Ref Target - Figure 2-36 13 12 11 10 Reg 4.24 X13708 Figure 2‐36: 10G PHY XGXS Lane Status Register XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 68 10G PHY XGXS Test Control register bit definitions. Table 2‐53: 10G PHY XGXS Test Control Register Bit Definitions Name Description Attributes Default Value 4.25.15:3 Reserved The block always returns 0 for these bits. All 0s XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 69 0 = Transmit test pattern disabled 11 = Reserved 10 = Mixed frequency test pattern Test Pattern 4.25.1:0 Select 01 = Low frequency test pattern 00 = High frequency test pattern XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...

  • Page 70: Use The Example Design As A Starting Point

    Nature of your application All XAUI implementations need careful attention to system performance requirements. Pipelining, logic mapping, placement constraints, and logic duplication are all methods that help boost system performance. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...

  • Page 71: Keep It Registered

    While registering signals might not be possible for all paths, it simplifies timing analysis and ® makes it easier for the Xilinx tools to place and route the design. Recognize Timing Critical Signals The supplied constraint file provided with the example design for the core identifies the critical signals and the timing constraints that should be applied.

  • Page 72: System Overview

    Ten Gigabit Ethernet Media Independent Interface (XGMII). Figure 4-1 shows the XAUI core being used to connect to a 10-Gigabit Expansion Pack (XPAK) optical module. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 73 X-Ref Target - Figure 4-2 FPGA FPGA Up to 20in FR-4 plus 2 connectors User XAUI XAUI User Logic Core Core Logic Backplane x13668 Figure 4‐2: Typical Backplane Application for XAUI XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...

  • Page 74: Functional Description

    A 2-wire low-speed serial interface used to manage the core. • Embedded FPGA transceivers. Provides high-speed transceivers as well as 8B/10B encode and decode, and elastic buffering in the receive datapath. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 75 Transceiver Lane 2 Synchronization Transceiver Lane 3 mdio Management Reference Clocks and clock Reset Logic clk156_out Reset X13667 Figure 4‐3: Architecture of the XAUI Core with Client-Side User Logic XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...

  • Page 76: Data Interface: Internal Xgmii Interfaces

    2. Table 5‐1: xgmii_txd, xgmii_rxd Lanes for Internal 64-bit Client-Side Interface Lane xgmii_txd, xgmii_rxd Bits 15:8 23:16 31:24 39:32 47:40 55:48 63:56 XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 77 Table 5-2 for reference. Table 5‐2: Partial List of XGMII Characters Data (Hex) Control Name, Abbreviation 00 to FF Data (D) Idle (I) Start (S) Terminate (T) Error (E) XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...

  • Page 78: Interfacing To The Transmit Client Interface

    XGMII idle characters. X-Ref Target - Figure 5-1 clk156 xgmii_txd[7:0] xgmii_txd[15:8] xgmii_txd[23:16] xgmii_txd[31:24] xgmii_txd[39:32] xgmii_txd[47:40] xgmii_txd[55:48] xgmii_txd[63:56] xgmii_txc[7:0] X13676 Figure 5‐1: Normal Frame Transmission Across the Internal 64-bit Client-Side I/F XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 79 The error code is denoted by the letter E, with the relevant control bits set. X-Ref Target - Figure 5-2 clk156 xgmii_txd[7:0] xgmii_txd[15:8] xgmii_txd[23:16] xgmii_txd[31:24] xgmii_txd[39:32] xgmii_txd[47:40] xgmii_txd[55:48] xgmii_txd[63:56] xgmii_txc[7:0] X13677 Figure 5‐2: Frame Transmission with Error Across Internal 64-bit Client-Side I/F XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...

  • Page 80: Interfacing To The Receive Client Interface

    Figure 5‐3: Frame Reception Across the Internal 64-bit Client Interface Figure 5-4 shows an inbound frame of data propagating an error. In this instance, the error is propagated in lanes 4 to 7, shown by the letter E. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 81 Chapter 5: Interfacing to the Core X-Ref Target - Figure 5-4 clk156 xgmii_rxd[7:0] xgmii_rxd[15:8] xgmii_rxd[23:16] xgmii_rxd[31:24] xgmii_rxd[39:32] xgmii_rxd[47:40] xgmii_rxd[55:48] xgmii_rxd[63:56] xgmii_rxc[7:0] X13675 Figure 5‐4: Frame Reception with Error Across the Internal 64-bit Client Interface XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...

  • Page 82: Configuration And Status Interfaces

    All transactions are initiated by the Station Management Entity (STA) entity. The XAUI core implements an MMD. X-Ref Target - Figure 5-5 MAC 1 MAC 2 mdio X13720 Figure 5‐5: A Typical MDIO-Managed System XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 83 3-state buffer as the bus interface. X-Ref Target - Figure 5-6 Virtex-7 XAUI Core IOBUF mdio_tri mdio_out mdio_in X13721 Figure 5‐6: Using a SelectIO Interface 3-State Buffer to Drive MDIO XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 84 In these sections, the following abbreviations apply: • PRE: preamble • ST: start • OP: operation code • PRTAD: port address • DEVAD: device address • TA: turnaround XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 85 0 1 P4 P3 P2 P1 P0 V4 V3 V2 V1 V0 1 0 D15 IDLE 32 bitsPREST PRTAD DEVAD 16-bit WRITE DATA IDLE X13722 Figure 5‐8: MDIO Write Transaction XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 86 1 0 P4 P3 P2 P1 P0 V4 V3 V2 V1 V0 Z 0 D15 IDLE 32 bitsPREST PRTAD DEVAD 16-bit READ DATA IDLE X13681 Figure 5‐10: MDIO Read-and-increment Transaction XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...

  • Page 87: Configuration And Status Vectors

    XAUI core. Enables transmit test pattern generation. See bit 5.25.2 in Test Enable Table 2-43. Test Select(1:0) Selects the test pattern. See bits 5.25.1:0 in Table 2-43. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 88 3 of the configuration vector. Figure 5-12 shows how the status bit is set. X-Ref Target - Figure 5-12 status_vector[7] (RX Link Status) configuration_vector[3] X13719 Figure 5‐12: Setting the RX Link Status Bit XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...

  • Page 89: Debug Port

    Each pin is 1 when the respective XAUI lane receiver is debug[4:1] synchronized to byte boundaries, 0 otherwise. Indicates when the TX phase alignment of the transceiver has been debug[0] completed. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...

  • Page 90: Shared Logic

    Vivado® IDE, as shown Figure 7-1. X-Ref Target - Figure 6-1 <component_name>_example_design <component_name> <component_name>_support <component_name>_block Shared Logic x13734 Figure 6‐1: Shared Logic Included in the Core XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...

  • Page 91: Clocking: Ultrascale Architecture

    For both 10G and 20G line rates, the reference clock frequency is selectable from the core IP customization interface. Available reference clock frequencies are: • 125 MHz • 156.25 MHz • 312.5 MHz XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 92 X-Ref Target - Figure 6-3 IBUFDS_GTE3 Shareable logic Figure 6‐3: Clock Scheme for Internal Client-Side Interface UltraScale Architecture GTH Transceiver Shared Logic in Example Design XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 93 See Figure 6-3 Figure 6-4 respectively for the shared logic to be included in the example design or in the core. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...

  • Page 94: Xaui V12.3 Product Guide Www.xilinx.com

    Chapter 6: Design Considerations X-Ref Target - Figure 6-5 IBUFDS_GTE3 Shareable logic Figure 6‐5: Clock Scheme for Internal Client-Side Interface UltraScale Architecture GTY Transceiver Shared Logic in Example Design XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 95 XAUI core, due to problems of phase alignment. For more information about UltraScale device transceiver clock distribution, see the UltraScale Architecture GTY Transceivers User Guide (UG578) [Ref 4] XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...

  • Page 96: Clocking: Zynq-7000, Virtex-7, Artix-7, And Kintex-7 Devices

    The transceivers require a reference clock of 156.25 MHz to operate at a line rate of 3.125 Gb/s. 20G — XAUI The transceivers require a reference clock of 312.5 MHz to operate at a line rate of 6.25 Gb/s. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 97 RXUSRCLK2 clk156_out BUFG clk156 Clock Logic TXOUTCLK BUFG dclk DCLK x13730 Figure 6‐7: Clock Scheme for Internal Client-Side Interface 7 Series FPGA GTH Transceiver Shared Logic in Example Design XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 98 XAUI core, due to problems of phase alignment. For more information about 7 series FPGA transceiver clock distribution, see the section on Clocking in the 7 Series FPGAs GTX/GTH Transceiver User Guide (UG476) [Ref XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 99 TXUSRCLK2 RXUSRCLK RXUSRCLK2 Clock Logic TXOUTCLK BUFG dclk DCLK x13733 Figure 6‐9: Clock Scheme for Internal Client-Side Interface 7 Series FPGA GTX Transceiver Shared Logic in Example Design XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 100 XAUI core, due to problems of phase alignment. For more information about 7 series FPGA transceiver clock distribution, see the section on Clocking in the 7 Series FPGAs GTX/GTH Transceiver User Guide (UG476) [Ref XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 101 TXUSRCLK2 RXUSRCLK RXUSRCLK2 Clock Logic TXOUTCLK BUFG dclk DCLK x13731 Figure 6‐11: Clock Scheme for Internal Client-Side Interface 7 Series FPGA GTP Transceiver Shared Logic in Example Design XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 102 XAUI core, due to problems of phase alignment. For more information about 7 series FPGA transceiver clock distribution, see the section on clocking in the 7 Series FPGAs GTP Transceiver User Guide (UG482) [Ref XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...

  • Page 103: Multiple Core Instances

    Receiver Termination: Virtex-7 and Kintex-7 FPGAs The receiver termination must be set correctly. The default setting is 2/3 VTTRX. See the Receiver chapter in the 7 Series FPGAs GTX/GTH Transceiver User Guide (UG476) [Ref XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...

  • Page 104: Transmit Skew

    802.3-2012. If it is necessary to keep within this skew budget, then the appropriate amount must be borrowed from the PCB and medium sections of the budget to keep the total amount of skew within range. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...

  • Page 105: Customizing And Generating The Core

    Vivado Design Suite User Guide: Getting Started (UG910) [Ref Figures in this chapter are illustrations of the Vivado IDE. This layout might vary from the Note: current version. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 106 This option is only available for UltraScale devices. Select the X/Y coordinate for the lowest numbered transceiver in the Quad that is used by the XAUI core. For example, selecting XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 107 PRBS. Shared Logic Tab Determines whether some shared clocking logic is being included as part of the core itself or as part of the example design. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 108 Data Rate Data_Rate TenGbps TenGbps TenGbps TwentyGbps TwentyGbps Shared Logic SupportLevel Include Shared Logic in core Include Shared Logic in example design Additional transceiver control and TransceiverControl false status ports XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...

  • Page 109: Output Generation

    DCLK clock must be provided and a constraint is required to specify its frequency: create_clock -name dclk -period 20.000 [get_ports dclk] XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 110 CompName :>_gt_i/*/gen_gtwizard_gthe3_top.<=: CompName :>_gt_gtwizard_gthe3_inst/ gen_gtwizard_gthe3.gen_channel_container[*].gen_enabled_channel.gthe3_channel_wrapp er_inst/channel_inst/ gthe3_channel_gen.gen_gthe3_channel_inst[2].GTHE3_CHANNEL_PRIM_INST ] set_property LOC GTHE3_CHANNEL_X0Y3 [get_cells xaui_support_i/xaui_i/inst/<=: CompName :>_gt_i/*/gen_gtwizard_gthe3_top.<=: CompName :>_gt_gtwizard_gthe3_inst/ gen_gtwizard_gthe3.gen_channel_container[*].gen_enabled_channel.gthe3_channel_wrapp er_inst/channel_inst/ gthe3_channel_gen.gen_gthe3_channel_inst[3].GTHE3_CHANNEL_PRIM_INST ] set_property LOC GTHE3_COMMON_X0Y0 [get_cells xaui_support_i/xaui_i/*/<=: CompName :>_gt_i/inst/gen_gtwizard_gthe3_top.<=: CompName :>_gt_gtwizard_gthe3_inst/ XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...

  • Page 111: Simulation

    Synthesis and Implementation For details about synthesis and implementation, see “Synthesizing IP” and “Implementing IP” in the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 112 All synthesis sources are included that are required by the core. For the XAUI core this is a mix of both encrypted and unencrypted source. Only the unencrypted sources are visible. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 113 Clocking COMMON component_name_clk_clocking.vhd/v Clock Logic component_name_gt_wrapper_gt.vhd/v Transceiver component_name_clk_resets.vhd/v component_name_gt_wrapper_gt.vhd/v Reset Logic Transceiver X13673 Figure 8‐1: Example HDL Wrapper for XAUI with Shared Logic in the Example Design (7-Series FPGAs) XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 114 Figure 8‐2: Example HDL Wrapper for XAUI with Shared Logic in Core (7-Series FPGAs) Figure 8-3 Figure 8-4 illustrate the top-level example design for the core with the two different configurations of the shared logic feature for UltraScale™ architecture. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...

  • Page 115: Chapter 8: Detailed Example Design

    (UltraScale wizard subcore) XAUI Encrypted HDL component_name_support_clocking.vhd/v Support Clocking component_name_clk_clocking.vhd/v Clock Logic component_name_clk_resets.vhd/v Reset Logic Figure 8‐3: Example HDL Wrapper for XAUI with Shared Logic in the Example Design (UltraScale Architecture) XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...

  • Page 116: Chapter 8: Detailed Example Design

    I/O pins. The example design can be opened in a separate project by generating the Examples' output product, then right clicking the core instance and choosing Open IP Example Design... XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 117 X-Ref Target - Figure 9-1 demo_tb <component_name>_example_design Transceivers XAUI Encrypted HDL Stimulus Monitor Clock Support Generation Clocking Clock Logic Monitor Stimulus Reset Logic MDIO Interface X13671 Figure 9‐1: Demonstration Test Bench XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...

  • Page 118: Chapter 9: Test Bench

    A watchdog timer is set to stop the simulation with a failure after 200 µs for GTX and GTH (20G XAUI) or 3 ms for GTP and GTH (10G XAUI) transceivers and 800 µs for UltraScale™ devices. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...

  • Page 119: Simulation

    Clock compensation • Recovery from error conditions Hardware Testing The core has been used in several hardware test platforms within Xilinx. In particular, the ® core has been used in a test platform design with the Xilinx 10-Gigabit Ethernet MAC core.

  • Page 120: Device Migration

    XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 121 Clock generated inside the txoutclk Rename to clk156_out port core Clock generated inside the txlock Rename to clk156_lock core Clock generated inside the mmcm_lock Port no longer required, remove connection. core XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 122 Used to share the core 156.25 MHz clock debug [5] previously named align_status, debug[4:1] previously Grouped all debug signals in debug[5:0] named sync_status[3:0] and one port debug[0] previously named mgt_tx_ready. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 123 Added Transceiver Control and Assign default value: '0' Status Ports gtN_txpolarity_in Added Transceiver Control and Assign default value: '0' Status Ports gtN_loopback_in Added Transceiver Control and Assign default value: B"000" Status Ports XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 124 Assign default value: open. Status Ports. Added Transceiver Control and gtN_txphinitdone_out Assign default value: open. Status Ports. Added Transceiver Control and gtN_txdlysresetdone_out Assign default value: open. Status Ports. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 125 Status Ports (7-Series families) Added Transceiver Control and gt_txinhibit[3:0] Assign default value: '0'. Status Ports (UltraScale architecture) Added Transceiver Control and gt_pcsrsvdin[63:0] Assign default value: '0'. Status Ports (UltraScale architecture) XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...

  • Page 126: Finding Help On Xilinx.com

    This product guide is the main document associated with the XAUI core. This guide, along with documentation related to all products that aid in the design process, can be found on the Xilinx Support web page or by using the Xilinx Documentation Navigator. Download the Xilinx Documentation Navigator from the Downloads page.

  • Page 127: Technical Support

    Answer Records Answer Records include information on commonly encountered problems, helpful information on how to resolve these problems, and any known issues with a Xilinx product. Answer Records are created and maintained daily ensuring that users have access to the most up-to-date information on Xilinx products.

  • Page 128: Debug Tools

    Captured signals can then be analyzed. This feature in the Vivado IDE is used for logic debugging and validation of a design running in Xilinx. The Vivado logic analyzer is used to interact with the logic debug LogiCORE™ IP cores, including: •...
  • Page 129 If problem is more design specific, open a case with Xilinx Technical Support Are you able to transmit and and include a wlf file dump of the simulation. recieve frames on the XGMII interface?

  • Page 130: Hardware Debug

    If the debug suggestions listed previously do not resolve the issue, open a support case to have the appropriate Xilinx expert assist with the issue. To create a technical support case in WebCase, see the Xilinx website at: www.xilinx.com/support/clearexpress/websupport.htm Items to include when opening a case: •...
  • Page 131 Problems with data reception or transmission can be caused by a wide range of factors. Following is a flow diagram of steps to debug the issue. Each of the steps are discussed in more detail in the following sections. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 132 Is the link status OK in loopback? Rate section below. See the General Checks section above. x13728 Figure C‐2: Flow Diagram for Debugging Problems with Data Reception or Transmission XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 133 When the MAC reconciliation layer receives a local fault, it silently drops any data being transmitted and instead transmits a remote fault to inform the link partner that it is in a fault condition. Be aware that the Xilinx 10GEMAC core has an option to disable remote fault transmission.
  • Page 134 Device B MAC reconciliation layer receives the remote fault. It silently drops any data being transmitted and instead transmits IDLEs. • Link Status = '0' (link down) in both A and B. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 135 X-Ref Target - Figure C-6 Device A Device B TX Idle Sequence Idle Sequence+RF RX Link Link MAC/XAUI MAC/XAUI RX Idle Sequence Idle SequenceTX X13727 Figure C‐6: Normal Operation XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 136 On the receive path the XAUI core will insert errors RXD=FE, RXC=1, when disparity errors or invalid data are received or if the received interframe gap (IFG) is too small. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 137 PCB issue. • Try swapping the optical module on a misperforming device and repeat the tests. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 138 XAUI core. • Verify in simulation and/or a Vivado lab tools capture that the waveform is correct for accessing the host interface for a MDIO read/write. XAUI v12.3 Product Guide www.xilinx.com Send Feedback PG053 April 6, 2016...
  • Page 139 If the debug suggestions listed previously do not resolve the issue, open a support case to have the appropriate Xilinx expert assist with the issue. To create a technical support case in Webcase, see the Xilinx website at: www.xilinx.com/support/clearexpress/websupport.htm Items to include when opening a case: •...

  • Page 140: Xilinx Resources

    For support resources such as Answers, Documentation, Downloads, and Forums, see Xilinx Support. References To search for Xilinx documentation, go to Xilinx Support web page 1. 7 Series FPGAs GTX/GTH Transceiver User Guide (UG476) 2. 7 Series FPGAs GTP Transceiver User Guide (UG482) 3.

  • Page 141: Additional Core Resources

    XAUI Technology For information about XAUI technology basics, including features, FAQs, the XAUI device interface, typical applications, specifications, and other important information, see www.xilinx.com/products/ipcenter/XAUI.htm. Ethernet Specifications Relevant XAUI IEEE standards, which can be downloaded in PDF format from standards.ieee.org/getieee802/: IEEE Std.

  • Page 142: Please Read: Important Legal Notices

    Xilinx's Terms of Sale which can be viewed at http://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance;...

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