Xilinx Zynq-7000 Design Manual page 3

Date Version
12/04/2013 1.6
08/01/2014 1.7
08/05/2014 1.7.1
11/07/2014 1.8
Zynq-7000 PCB Design Guide
UG933 (v1.8) November 7, 2014
Changed "DDR3" to "DDR3/3L" throughout document. Updated capacitor quantities
and packages in Table 3-1
Table 3-3. Updated descriptions for
PS Auxiliary Logic Supply. Deleted "Capacitor Consolidation Rules" section. Modified
next-to-last sentence under
Voltage. Added paragraph preceding
Command, Contrl output name in
Length.
Removed "and Pin Planning Guide" from title. Added recommendation to
Recommended PCB Capacitors per
"100 µF" to 47 µF" in Table
reference (Note 3) in Table
added "X7U" to 100 µF capacitor in
Limits by removing specifications and adding a reference to the data sheet. Updated
second paragraph under Unconnected V
"GRM155R60J475ME47D" to "GRM155R60J474KE19" under
Updated first paragraph under
Voltage. Updated Unused DDR
– Power on Reset and last sentence under
Changed "Boot Mode Pins" section (pins MIO[2] to MIO[8] to
Modified Figure 5-5 (CKE resistor layout). Modified
differential signals CLK_P/CLK_N and added pull-down resistor to ODT). Added
separate column for DDR3L to
Length and DDR Trace Impedance
Routing Topology. Added last paragraph under
Operating Frequencies (without Feedback Mode)" section from
Updated document to latest user guide template.
Added XC7Z035 device to
Updated Table 5-5.
www.xilinx.com
Revision
and Table 3-2. Updated capacitor specifications in
V – PS Internal Logic Supply
CCPINT
PS_DDR_VREF0, PS_DDR_VREF1 – PS DDR Reference
Table 5-5 and updated
Figure 5-7. Deleted last sentence under
Device. Changed V
3-1. Removed values for V
3-2. Changed "Terminal" type to "Terminal Tantalum" and
Table 3-3. Modified first paragraph under
Pins. Changed Murata part number from
CCO
PS_DDR_VRN, PS_DDR_VRP – PS DDR Termination
Memory. Deleted last two sentences under
PS_SRST_B – External System
Figure 5-6
Table 5-6 and modified values. Clarified
sections. Clarified byte swapping under
Ethernet
Table 3-1 and Table 3-2. Added 10
and V
CCPAUX
Table 5-5. Updated Addr,
DDR Trace
per Bank sub-heading from
CCO
and replaced with
CCPLL
Noise
Unconnected V
CCO
PS_POR_B
Reset.
Boot Mode Pin MIO[8].
(changed clk signal to
DDR Trace
DDR
GEM. Deleted "Lower
Chapter 6.
Table
µF capacitor to
Send Feedback
–
Pins.
3-3.
3