Intel Agilex User Manual page 9

3. Intel Agilex Power and I/O State Sequencing
UG-20215 | 2019.04.02
Table 2. Voltage Rails Group
Power Group
All power rails in Group 1 must ramp up (in any order) to a minimum of 90% of their
respective nominal voltage before the power rails from Group 2 can start ramping up.
The power rails within Group 2 can ramp up in any order after the last power rail in
Group 1 ramps to the minimum threshold of 90% of its nominal voltage. All power
rails in Group 2 must ramp to a minimum threshold of 90% of their nominal value
before the Group 3 power rails can start ramping up. The power rails within Group 3
can ramp up in any order after the last power rail in Group 2 ramps up to a minimum
threshold of 90% of their full value. For more information, refer to the Intel Agilex
Device Family Pin Connection Guidelines.
All power rails must ramp up monotonically. The power-up sequence must meet the
POR delay time. For the POR specifications of the Intel Agilex devices, refer to the POR
Specifications section in the Intel Agilex Device Data Sheet.
For configuration via protocol (CvP), the total t
first power supply ramp-up to the last power supply ramp-up. For the t
specifications, refer to the Recommended Operating Conditions section in the Intel
Agilex Device Data Sheet.
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Group 1
Group 2
Group 3
Intel Agilex
V
CC
V
CCP
V
CCH
V
CCL_SDM
V
CCH_SDM
V
CCPLLDIG_SDM
V
CCL_HPS
V
CCPLLDIG_HPS
E-tile
V
CCRT_GXE
V
CCRTPLL_CR3_GXE
P-tile
V
CC_HSSI_GXP
V
CCRT_GXP
V
CCFUSE_GXP
V
CCPT
V
CCA_PLL
V
CCPLL_SDM
V
CCADC
V
CCPLL_HPS
V
CCM_WORD
E-tile
V
CCH_GXE
V
CCCLK_GXE
P-tile
V
CCH_GXP
V
CCCLK_GXP
V
CCIO_PIO
V
CCFUSEWR_SDM
V
CCIO_SDM
V
CCIO_HPS
must be less than 10 ms from the
RAMP
® ™
Intel Agilex
RAMP
Power Management User Guide
9