Festo CPX-FVDA-P2 Original Instructions Manual page 36

System overview CPX-FVDA-P2
Bit pattern of the input data: byte 0 and byte 1
Byte Bit 7
Byte 0 Reserved
0
Byte 1 Channel-
wise pas-
sivation
0 = Off
1 = On
1) These bits reflect the logical actual statuses. The statuses are not determined through measurements. No external voltages are evalu-
ated at passivated or switched-off outputs. If the complete module is passivated, these bits deliver 0 signals. If an output channel is
passivated, the corresponding bit delivers a 0 signal.
Tab. 21 Bit pattern of the input data (F-user data, byte 0 and byte 1)
Acknowledgment sequence
If channel-wise passivation is used, acknowledgement must be ensured via the user program.
The following sequence description
(è Tab. 22 Sequence description of channel error acknowledgment – example) shows the relevant
bits for channel-wise passivation in the input and output images of the module
(è Tab. 20 Bit pattern of the output data (F-user data, byte 0 and byte 1)),
(è Tab. 21 Bit pattern of the input data (F-user data, byte 0 and byte 1)).
No. Sequence
1 Module is not passiv-
ated
Channel error occurs
2 Module has detected
the error
F-Host detects the
error in the module
36
Bit 6 Bit 5
Test pulses activ-
ated
CH2 CH1
0 = Activate
1 = Deactivate
Reserved
0
Channel- Target
wise passiv- status of the
ation output
1)
channel
1 (active) X
1 (active) X
Bit 4 Bit 3
Reserved
0
Data dir- Reserved
ection
0 = 0
Device to
Host
(fixed
value)
Actual
status of the
output
1)
channel
2)
X
0
3)
Bit 2 Bit 1
Logical actual status
1)
CH2 CH1
0 = Off
1 = On
Channel error status
CH2 CH1
0 = No error
1 = Error
Channel Acknow-
error ledgment of
2)
status channel
error
0 0
3)
1 0
Festo — CPX-FVDA-P2 — 2018-10b
Bit 0
CH0
CH0
1)