Holdoff Counter Encoding - Tektronix 2246 1Y Service Manual

Theory of Operation—2246 1Y and 2246 Mod A Service
H4 H3 H2 HI
0 0 0
0
0 0 0 0
0 1
0 0
1
0 0 0
0 0 1 0
1
0 0 0
1 1
0 0
1 1
0 0
1 0 0
0
1 0 0
0
1 0 1
0
1 0 1
0
0 1 1 0
1 1 0
0
1 1 1
0
0 1 1 1
a Strobing RESET presets the holdoff counter to 499999 to simplify testing.
DD: Dual-delay control bit. DD = 1 for dual
delay (delta tim e), and DD = 0 for single
delay.
SSE: SGL SEQ enable. SSE = 1 for single
sequence mode or 0 for repetitive mode.
B ENDS A: B ends A enable (active high).
H4, H3, H2, H I, HO: Holdoff time. Encoded
as in Table 3-14. With the TEST pin held
high for normal operation.)
FSEL: Chop frequency select bit. With 10
MHz on the TC input pin, FSEL = 1 provides
a chop frequency of 625 kHz; FSEL = 0
produces 1.25 MHz (625 kHz is used).
3-22
Table 3-14

Holdoff Counter Encoding

Count Length
HO
1
0
1 2
0 5
1 5
0 10
1 20
0
50
1
50
100
0
1 200
0
500
1
500
0
1000
1
2000
0 5000
1 5000
H4 H3 H2 HI
1 0 0 0
1 0 0 0
1 1
0 0
1
1 0 0
1 0 1 0
1 1
0 0
1 1 1
0
1 1
1 0
1 0 0
1
1 0 0
1
1 1 1
0
1 1
0
1
1 1 1 0
1 1 1 0
1 1 1
1
1 1 1 1
CBEN: Chop blank enable bit. CBEN = 1
allows the chop blanking signal to be passed
out the BLANK output pin (when ROR is
high); CBEN = 0 inhibits chop blanking.
Display Sequencer Operation
The internal RAM is programmed for the desired
vertical channel display sequence, for both CHOP
and ALT Vertical Modes. In ALT mode, the RAM also
controls the horizontal display control outputs. In
CHOP mode, the RAM still controls the vertical
channel displays, but different logic controls the
horizontal display selection.
RAM data bits RD5, RD4, and RD3 are programmed
for a particular channel display (see Table 3-15).
Count Length
HO
10000
0
1 20000
0 50000
1 50000
0 100000
1 200000
0
500000
1
500000
0 100000
1 200000
0
500000
1
500000
0
100000
1 200000
500000
0
1 1a