Display Sequencer 1C (Slic, U600); Pin-Out D Ia G Ra M - Tektronix 2246 1Y Service Manual

Theory of Operation—2246 1Y and 2246 Mod A Service
cannot move the voltage on U1102B pin 5 across the
comparison threshold (ground on pin 6).
During the vertical field sync pulse, the frequency of
the serration pulses (line and equalizing) doubles.
The filter capacitors will then be discharged enough
to go below ground and switch the output state of
U1102B. That signal is applied to U1104A pin 1 to be
available as the TV FIELD Sync trigger signal for the
A Trigger system.
SYNC SWITCHING. Solid-state switches U1104A
and U1106C provide switching between the TV FIELD
and the TV LINE signal for the A Trigger and between
TV LINE from A SOURCE and the average DC level of
the measurement channel for the B Trigger. The
switching states are controlled by the Measurement
Processor via the TV FIELD SEL and the B TV TRIG
EN control signals from the Auxiliary Control Register
(U1103).
DISPLAY AND TRIGGER LOGIC AND
PROCESSOR INTERFACE (Diagram 4)
The Display Sequencer or SLIC (slow-logic inte­
grated circuit, U600) performs most of the slow
logic functions required to run the display functions.
This integrated circuit contains a microprocessor
interface, the display sequencer logic circuitry, the
trigger holdoff timer, the chop clock, and an inter­
face to the on-screen readout control logic.
The microprocessor interface of U600 provides the
capability to serially
register, write the internal read/write memory, do
some limited real-tim e control over a few sequencer
functions, and monitor status information.
The Display Sequencer
memory for storing the
sequenced through and logic for sequencing the A
and B Sweep displays and trigger sources. The
sequencer also provides control signals that are
needed to do waveform measurements.
An internal trigger holdoff tim er provides a pulse with
programmable width that is triggered on at the end
of A Sweep (or at the end of B Sweep). The pulse
width may be set from 1
depending on the internal counter divide ratio, and
the holdoff oscillator frequency at pin 15.
The chop clock circuit generates a phase-dithered
chop clock and blanking signal, derived from an
external frequency source. With 10 MHz applied, the
chop rate can be 1.25 MHz or 625 kHz, with a
blanking time of about 200 ns (625 kHz is used in the
2246 1Y and 2246 Mod A).
3-16
load the internal control
contains a read/write
display states to
.
to greater than 0.5 s,
jj s
The readout interface
readout request and readout blanking inputs, and
generates a blanking signal (BLANK, pin 18) to
control the Z-Axis Amplifier enabling signals from
U602. The chop blanking signal also gets routed
through this circuit.
Pin Description
The following is a description of Display Sequencer
U600 pin functions
num bers).
i
TC
2
LFC
3
WR
4
A0
5
A1
6
A2
7
A3
8
RD
g
DIO
10
TDI
l i
R0R
12
ROB
13
B GATE
be
14
A GATE
15
0SC0UT
16
0SCRST
17
TH0
18
BLANK
19
S0UT
20
vss
Figure 3-1. Display Sequencer 1C (SLIC, U600)
p in -o u t diagram.
circuit responds to the
(see Figure 3-1 for
40
V DO
39
CH 1 EN
38
CH 2 EN
37
CH 3 EN
36
CH 4 EN
D
35
I
MGE
s
34
P ZEN
33
L
ATS 2
A
32
Y
ATS 1
31
ATS 0
S
30
t
A SLOPE
Q
29
BTS 2
U
28
E
BTS 1
N
27
BTS 0
C
26
E
B SLOPE
R
25
OS
(SLIC)
24
HD0
23
HD1
22
TS
21
TEST
6081 04 6555-31
( - )
pin