Display Addresses - Tektronix 2246 1Y Service Manual

Theory of Operation—2246 1Y and 2246 Mod A Service
address lines defines either text (menus, measure­
ment readouts, and error
cursors, or horizontal cursors. Each field has space
for up to 255 characters, and each field is super­
imposed over the others on the crt. The difference
between vertical and horizontal orientation of the
cursors types is done by rotating the character field
90 degrees. Hexadecimal addresses for a field are
shown in Figure 3-7.
eO |
cO w
LU
CD
a0
u j
DC
Q
80 §
CD
60 5
CD
40 w
CJ
20 2
00 I N C R E A S I N G A D D R E S S E S — ►
Figure 3-7. Display addresses.
Character Dot Counter
The Character Dot Counter (U2407A and B) is reset
before t he start of each character display. When
RO RUN goes low (the start of a refresh cycle ), the
reset is released and the clock signal from the Dot
Refresher (U2410) clocks the output of the counter
through the number of counts needed to address all
the dots in a character stored in the Character Dot
Position ROM (U2408).
Character Dot Position ROM
The dot sequence and dot position to display each
character is stored in the Character Dot Position
ROM (U2408). Character addressing for the display
is provided by the Character Codes RAM (U2406) on
the R0-R6 bus lines. Addressing of the individual
dots within a character is provided from the Charac­
ter Dot Counter (U2407A and U2407B) on the
DOTO-DOT4 signal lines. The pixel information out­
put by the Character Dot Position ROM defines the
vertical and horizontal position of the dot to be dis-
played. At the end of a character display, the EOCH
signal is generated from U2408 pin 17 to the Dot
Refresher (U2410) to let that device know that the
3-48
messages), vertical
f f
df
bf
9f
7f
5f
3 f
If
6081-10
character is finished and the next character can be
started.
Dot Refresher
Dot Refresher U2410 is a programmable-AND,
fixed-OR logic (PAL) device. It monitors RO RUN for
its low states to determine when a refresh cycle
starts. It then assert RO REQ to take control of the
display for refreshing the displayed character dots.
RO BLANK goes high then low again for each dis­
played dot. The clock signal then goes low and high
again to clock the Character Dot Counter (U2407A
and U2407B) to the address of the next dot in the
character being refreshed. In Fast mode (when
there is low demand for display time or the refresh
rate is getting too slow), each character is com­
pletely refreshed. In Slow mode, the dots are
refreshed at the rate of only one dot per each
readout request.
When all the dots in a character have been
refreshed, the EOCH
from Character Dot Position ROM U2408 tells U2410
that there are no more pixels to be refreshed in that
character. RO REQ is then unasserted to release
control of the display system and Q EOCH (U2410,
pin 18) is sent to the Readout Processor to tell it that
the Dot Refresher is finished with the character.
The Dot Refresher also asserts the POS EN signal
low (pin 19) when readout associated with any of the
traces is being displayed. That signal enables the
Readout Position Enable Latch (U2403).
Divider/Counter
The 8 MHz System Clock is divided down to 4 MHz
by Divider/Counter U2409A for clocking the Readout
Processor and to 2 MHz to clock the Dot Refresher
(after inversion by U2417B). The 2 MHz signal also
clocks U2409B, a second divider that produces the
signals that cycle the Dot Refresher through its
internal states.
Readout Position Enable Latch
When the readouts must follow the Channel Vertical
POSITION controls or the TRACE SEP control, the
vertical position information must be added to the
readout position. This job is done in the Vertical
Position Switching circuitry (Diagram 2). The time of
enabling and the readout position that is enabled is
determined by the Readout Processor. The correct
enabling data for the next field of characters to be
displayed is latched into U2403 from the R0-R7 (bits
0 -4 only) bus by the POS STB signal (U2403, pin
(end-of-character) signal