A Trigger Source Select Bits; Horizontal Display Mode Select Bits - Tektronix 2246 1Y Service Manual

ATS 2, ATS 1, ATS 0: A Trigger Source
Select outputs. These bits either correspond
to three bits of the control register, or they
track with the vertical channel enable out­
puts (in ALT Vertical Mode with VERT MODE
trigger selected). These outputs change
state on the rising edge of the THO output,
or when RESET is strobed while THO is high.
The encoding scheme is shown in Table 3-8.
Table 3-8
A T rigger Source Select Bits
ATS 2 ATS 1 ATS 0
0
0 0
0 0 1
0 1 0
0 1 1
1 0
0
1 0 1
A SLOPE: A Trigger slope output.
BTS 2, BTS 1, BTS 0: B Trigger Source
Select outputs. These bits correspond to
either one of two sets of three bits in the
control register, or they can track with the
vertical channel enable outputs
Vertical MODE). These outputs normally
change state on the rising edge of the THO
output, or when RESET is strobed while THO
is high. If B1 or B2 Source/Slope/Delay is
being forced, the outputs will correspond
directly with one of the two three-bit sets in
the control register. The encoding scheme
matches that used for the A trigger source
select bits shown in Table 3-8.
B SLOPE: B Trigger Slope output. This out­
put is set to either one of two bits in the con­
trol register. This output normally changes
state on the rising edge of the THO output,
or when RESET is strobed while THO is high.
It may also be forced high or low by the
Measurement Processor via the processor
interface.
HD1, HDO: Horizontal display enable out­
puts. These outputs normally change state
on the rising edge of the THO output, or
when RESET is strobed while THO is high.
The encoding scheme is shown in Table 3-9.
Theory of Operation—2246 1Y and 2246 Mod A Service
SOURCE
CH 1
CH 2
CH 1 + CH 2
CH 3
CH 4
Line
(in ALT
Table 3-9

Horizontal Display Mode Select Bits

HD1
HDO
0 0
1
0
1 0
1 1
DS: Delay select output.
normally changes state on the rising edge of
the THO output, or when RESET is strobed
while THO is high. It may also be forced by
the Measurement Processor
processor interface. DS high selects the first
delay (B1), and DS low selects the second
delay (B2).
TS: Trace separation output. This output
changes state on the rising edge of the THO
output, or when RESET is strobed while THO
is high. TS goes high to enable trace
separation; TS goes low during a readout
request cycle.
ZEN: Z-Axis enable output (active low). This
output goes low when the ZAP control bit is
set high, or when the selected B trigger
source channel (as presented on the BTS 2,
BTS 1, and BTS 0 output pins) is the same
as the channel being enabled for display.
M G E: Measurement gate enable output
(active low ). This output behaves the same
way as ZEN, except in chop vertical mode,
in which MGE stays in a low state. Also, the
ZAP control bit has no effect on MGE.
THO: Trigger holdoff output (active high).
Outputs the variable holdoff pulse. In single
sequence mode, this output will go high
after the last A Sweep of the sequence and
stay high until RESET is strobed. This output
may also be forced high via the Measure­
ment Processor interface.
BLANK: This output is controlled from three
sources. At the end of a readout request
cycle (when ROR goes high), the BLANK
output will be asserted for four to six timing
clock periods (to hide
switching transients). Chop blanking pulses
can be routed to this output (however, when
ROR is low, chop blanking is automatically
SOURCE
Readout displayed
A Sweep displayed
B Sweep displayed
X -Y mode
This output
via the
vertical source
3-19