Vertical Preamps And Output Amplifier; A And B Trigger System - Tektronix 2246 1Y Service Manual

Theory of Operation—2246 1Y and 2246 Mod A Service
Scaling of the Channel 1 and Channel 2 signals is
done by a series of switchable attenuators that pro­
vide either no attenuation, X I 0 attenuation, or X I 00
attenuation of the input signal. A low-impedance
attenuator following an input signal buffer produces
X I , X2, and X5 attenuation steps. Additional control
of input signal scaling is provided by the selectable
gain Vertical Preamplifiers (shown in Diagram 2).
Channel 3 and Channel 4 input signals are buffered
by high input impedance FET amplifiers; no input
attenuation of the signal is provided. The gain
choices for Channel 3 and Channel 4 are selected by
the choice of Vertical Preamplifier gain setting only.
The Measurement Processor controls the operation
of much of the switchable circuitry of the 2246 1Y
and 2246 Mod A via a common shift register data
line (SR DATA). Data bits loaded into the attenuator
control and gain shift register (designated SRO) set
the magnetic relay switches for the input coupling
and attenuator settings and select the gain settings
of the Preamplifiers.
VERTICAL PREAMPS AND OUTPUT
AMPLIFIER (Diagram 2)
Each vertical channel has identical selectable-gain
Preamplifiers. The calibrated
manually set during adjustment. Enabling of the
Preamplifiers to display a channel input signal is con­
trolled by the SLIC Display Logic (U600, Diagram 4).
Preamplifier gain settings are controlled by the
Measurement Processor via control bits loaded into
the attenuator control
(Diagram 1). Vertical channel trigger signal outputs
are produced by each of the Preamplifiers for trig­
gering the sweep from the applied signal.
The vertical outputs of each preamplifier are con­
nected to a summing node at the input to the Delay-
Line Driver. There, the signal current (from the
enabled Preamplifiers) and the no-signal standing
currents (from the disabled Preamplifiers) are added
with the current from the position signal switching
circuit.
The signal current for the enabled channel (vertical
channel signal plus its position offset) or the readout
position current (enabled to the summing node
during text and cursor displays) is applied to the
Delay-Line Driver. There,
3 -2
gain for each is
and gain shift register
it is buffered and
compensated to drive the vertical delay line. The
delay line produces enough delay in the signal to
permit the trigger circuitry to start the sweep before
the vertical signal arrives at the crt deflection plates,
and the rising edge of the triggering signal may be
viewed.
From the output of the delay line, the signals are
applied to the Vertical Output integrated circuit. The
Vertical Output 1C (U701) has provisions for vertical
BEAM FIND, bandwidth limiting,
readout display jitter. External filter elements on the
Vertical Output 1C produce the bandwidth limiting
when switched into the amplifier circuitry. The output
signal from U701 is then applied to the Vertical Out­
put Amplifier where it gets its final boost in power to
drive the vertical crt deflection plates.
An auxiliary Vertical Comparator circuit (U702 and
Q703) is shown in Diagram 2. Its purpose is to
measure the gains and offsets during SELF CAL to
determine the vertical calibration constants needed
for the measurements and tracking cursor displays.
A AND B TRIGGER SYSTEM (Diagram 3)
The A and B Trigger System provides the circuitry
for trigger source, slope, coupling, and bandwidth
selection; trigger level comparison; tv trigger detec­
tion; and dc measurements of the measurement
source signal.
Trigger selection signals from the Display Logic 1C
(U600, Diagram 4) drive the switching circuitry
internal to U421 and U431. The signals select the
correct trigger source, slope, and coupling choice
for the present front-panel control setting. For VERT
MODE triggering with more than one vertical channel
displayed, the trigger source selection changes as
each channel is displayed. When the ADD Vertical
Mode is selected, a special amplifier arrangement in
U421 (for A) or U431 (for B) sums the CH 1 and
CH 2 signals to provide an ADD trigger signal for
display of the ADD waveform.
The Trigger CPLG (coupling) selections are AC, DC,
HF REJ (high-frequency re je ct), LF REJ (low-
frequency reject), and NOISE REJ. Of these, ail but
NOISE REJ coupling are produced by selecting a
filter path with the necessary bandwidth character­
istics. NOISE REJ coupling is done in the Trigger
Level Comparator circuit by decreasing the sensi­
tivity of the comparator.
vertical gain, and