A And B Sweeps And Delay Comparators (Diagram 5); Horizontal Output Amplifier (Diagram 6 ); Z-Axis, Crt, Probe Adjust, And Control Mux (Diagram 7) - Tektronix 2246 1Y Service Manual

Theory of Operation—2246 1Y and 2246 Mod A Service
A AND B SWEEPS AND DELAY
COMPARATORS (Diagram 5)
The A and B Sweep circuitry sets the timing and
produces the A and B ramp signals to drive the crt
horizontal deflection plates. The Measurement Pro­
cessor sets the hardware states using control bits
loaded into shift register 1. One register (U302)
holds the bits for selecting the A Sweep timing
resistors and capacitors and one register (U303)
holds the B Sweep control bits. The timing resistors
are selected by multiplexers (U307 and U308 for A
Sweep timing; U310 and U311 for B Sweep timing)
that are switched by the states of the control bits;
timing capacitors are selected directly by the control
bits.
The starting level of the sweeps is held steady by a
Baseline Stabilizing circuit, and the sweep ends are
determined by two Sweep-End Comparators. A and
B GATE signals from the Trigger Logic 1C (U602,
Diagram 4) control the start of the sweep ramps. A
constant charging current to the timing capacitors
produces a linear voltage rise across the capacitors.
That voltage is buffered by the A and B Sweep
Buffers for application to the Horizontal Output
Amplifier (Diagram 6).
The SEC/DIV VAR control, when out of the calibrated
detent position, changes
delivered to the sweep timing capacitors
portional to its rotation. Decreasing the current
lengthens the ramp to decrease the sweep speed.
Two comparator circuits are used to check the A
Sweep ramp amplitude against the Reference Delay
and Delta Delay voltages. Both Delay End Com­
parator outputs are applied to the Trigger Logic 1C
(U602, Diagram 4). The Trigger Logic 1C monitors
the delays to determine when the B Sweep may
either run (for RUNS AFTER B Trigger Mode) or
accept a B Trigger (for any of the triggered B Sweep
m odes).
HORIZONTAL OUTPUT AMPLIFIER
(Diagram 6)
Deflection signals applied to the Horizontal Pre­
amplifier (U802) are the A Sweep Ramp, the B
Sweep Ramp, the horizontal readout, and the X-Axis
input signal for X -Y displays. Mode control signals
HDO and HD1 (from Display Logic 1C U600 to the
Horizontal Preamplifier) select the horizontal display
mode (A Sweep, B Sweep,
display). Other control signals to the Horizontal
Preamplifier are the MAG signal (for X I 0 magni­
fication of the sw eep), the BEAM FIND signal
3-4
the charging current
pro­
Readout, or X-Y
(decreases horizontal gain), and the horizontal
position signal for positioning the display. The X-Y
signal controlling U301B reduces the range of the
Horizontal POSITION signal delivered to the Hori­
zontal Preamplifier when in the X-Y display mode.
Five manual adjustments are associated with the
Horizontal Preamplifier. They are the X I 0 and XI
gain, the Readout gain, the X-Axis signal gain, and
Mag Registration. Mag Registration compensates for
offset between X I 0 and XI gains, but it is primarily
used to center the readout displays horizontally.
The active single-ended deflection signal input to
the Horizontal Preamplifier is amplified and con­
verted to a differential output signal. That signal is
further amplified and compensated by the Horizontal
Output Amplifier to drive the horizontal deflection
plates of the crt. The final output amplifier consists
of four MOSFET transistors (Q801, Q802, 0805, and
Q806). Two transistors are used for each deflection
plate (left and right) to divide the power handling
requirements.
Z-AXIS, CRT, PROBE ADJUST, AND
CONTROL MUX (Diagram 7)
This block of circuitry is divided into several different
functions. The largest division is the Z-Axis and CRT
circuitry. A INTEN, B INTEN, and RO INTEN input sig­
nals are applied to the Z-Axis circuit to set the
associated display intensities. Enabling gates from
the Display Controller
appropriate Z-Axis input signal for application to the
Z-Axis amplifier as the different display types are
enabled. The amplified Z-Axis signals are then level
shifted to the negative voltage of the crt cathode
(-2.7 kV) in a dc restorer circuit. A similar dc
restorer circuit provides auto focusing (at the fixed
focus level set by the front panel FOCUS control) in
response to the intensity
intensity and auto focus control voltages are applied
to the crt where they modulate the electron beam
flow that produces the display seen on the screen.
Multiplexer U506, under control of the Measurement
Processor, scans the
potentiometers and the probe code lines to check
for a change. Signal selection for routing through the
multiplexer is controlled by the three bits on the
POT5-POT7 bus lines from the Pot Data Latch
(Diagram 11). Output from the multiplexer is routed
to the Front-Panel Multiplexer (U2309, Diagram 11)
and multiplexed with other front-panel control levels.
Outputs from U2309 are routed to the A -to-D
Converter (U2306, Diagram 11) where a digital value
representing their analog
determined. That value is checked against the pre­
viously obtained value for a selected potentiometer
(Diagram 4) select the
level changes. The
front panel intensity
voltage level is