Display Sequencer (U600) Control Bit Assignments - Tektronix 2246 1Y Service Manual

Theory of Operation—2246 1Y and 2246 Mod A Service
A2 A1
A3
0 0 0
0 0 0
0 0 1
0 0 1
1
0 0
0 1 0
1 1
0
1 1
0
1
0 0
1
0 0
1 0 1
1 0 1
1 1 0
1 1 0
1 1 1
1 1 1
Notes:
(a) Data is clocked into the control register on the rising edge of WR.
(b) RAM load mode must be enabled; the address Increments on the rising edge of WR.
(c) EOS (end of sequence) goes high fo r the last state of any display sequence. EOS is read out for test purposes.
(d) The THO output should be set high when RESET is strobed fo r proper initialization. This does the following:
a. It initializes the display sequencer back to the first display state (RAM address 000). In ALT VERT Mode, all verti­
cal enable, horizontal enable, and trig source outputs are initialized, in CHOP VERT Mode, the horizontal enable
and trig source outputs are initialized, but the vertical enable outputs continue to cycle at the chop clock rate.
b. It resets the EOSS (end of single sequence) flag.
c. It resets the trigger holdoff tim er.
(e) Used fo r initialization, during testing of the device.
(f) A rising edge on WR with DIO = 1 enables the RAM load mode; a rising edge on WR with DIO = 0 disables the RAM load
mode.
(g) A rising edge on WR with DIO = 1 sets the A Slope output high; a rising edge on WR with DIO = 0 sets the A Slope
output low.
(h) Used fo r device testing only.
(i) A rising edge on WR with DIO = 1 forces the B1 Trigger Source, the B1 Slope, and sets the DS output high; a rising
edge on WR with DIO = 0 forces the B2 Trigger Source, the B2 Slope, and sets the DS output low.
(j) A rising edge on WR with DIO = 1 forces the B SLOPE output high; a rising edge on WR with DIO = 0 forces the B
SLOPE output low. This forcing
scribed in note (i) above. This forcing function is canceled by applying a negative strobe to the WR input with the
address = 1110.
(k) A rising edge on WR with DIO = 1 sets the output high; a rising edge on WR with DIO = 0 allows the output to behave
normally.
( ) A negative pulse on WR with address = 1110 will cancel the effects of (i) above and allow the B Source, B Slope, and
l
DS outputs to behave normally.
3-18
Table 3-7

Display Sequencer (U600) Control Bit Assignments

A0
DIO when RD LO
0 Control Reg. msb
1 RAM comparator
0 EOSS flag
1
EOS signal (c)
A Gate Detect flag
0
1 B Gate Detect flag
0 A Gate Detect flag
1 B Gate Detect flag
(h)
0
(h)
1
(h)
0
(h)
1
0 TDI data
1
TDI data
0 TDI data
1 TDI data
function takes precedence over the force B1/B2 S ource/Slope/Delay feature de­
Action when WR Strobed
DIO clocked into Control Reg. (a)
RAM written from Control Reg.
RAM address incremented (b)
RESET is strobed (d)
MRESET is strobed (e)
RAM load mode enabled (f )
A/B GATE-detected flags reset
Set A slope output (g)
Forces B1/B2 Source/Slope/Delay (0
Forces B Slope output (I)
Sets BLANK output HI (k)
Sets THO output HI (k)
(see description of TEST input)
(see description of TEST input)
Sets norm B Source/Slope/Delay I1 )
SOUT pin gets strobed