Control Register Signal-Bit Names; Delay Mode Selection Control Bits; Peak Volts Detection Mode Logic - Tektronix 2246 1Y Service Manual

Theory of Operation—2246 1Y and 2246 Mod A Service
Table 3-18

Control Register Signal-bit Names

Bit
1
2
3
4
5
6
7
8
Table 3-19

Delay Mode Selection Control Bits

DM1 DM0 Delay Mode
0 0 First delay set to zero
0 1 First and second delays set to zero
1 0 Normal delay mode
1 1 B Sweep disabled
Table 3-20

Peak Volts Detection Mode Logic

PM1 PMO Peak Detection Mode
0
0 Nongated
Gated from end of delay to
0 1
end of A Sweep
1
Gated with C GATE3
0
1
1 Gated with A GATE
C GATE not used externally in 2246A.
ZM1, ZMO: These bits determine the intensi­
fied zone mode. See the Z-Axis logic
discussion.
3-28
Name
DM0
A Sweep Logic
DM1
When ARUN is high, the A Sweep logic works as fol­
lows. A high on the THO input causes the A GATE
BRUN
output to go low. As soon as THO goes low, the A
GATE output will go high and the A Sweep runs. At
PMO the end of the A Sweep there is a low-to-high tran­
sition on the EOAS input. That sets the the internal
PM1
end-of-A -sw eep latch causing the A GATE output to
go low, and the A Sweep shuts off. This state exists
during sweep retrace and the baseline stabilization
ZMO
period until the end of holdoff when the THO input
ZM1 once
end-of-A -sw eep latch and starts another A Sweep
ARUN cycle. Normally, the falling edge of A GATE will
cause an externally generated pulse to be presented
on the THO input, thus completing the loop and
allowing the A Sweep to free-run (auto-level and
auto triggered
triggered).
When ARUN is low, the operation is similar except
that after a pulse on the THO input, A GATE won't go
high until a low -to-high transition is presented on
the A TRIG input (triggered sweep m ode).
For either free-run or triggered modes, THO going
high will cause the A GATE output to immediately go
low, if the end-of-A -S w eep latch is set or not. Once
the end-of-A -S w eep latch has been set, no more A
Sweeps can happen until the THO input is pulsed (at
the end of the holdoff). The end-of-A -S w eep latch
can only be set with the EOAS input when A GATE is
high.
The A Sweep logic of U602 also monitors the A TRIG
input to latch certain A Trigger events. One latch
(the auto-baseline latch) will set on any low-to-high
transition on the A TRIG input. Another latch (the A
Trigger latch) is level sensitive and will set when the
A TRIG input is high. Both latches may be read out
through the TDO (trigger-data out) pin, selected by
the A1 and AO address input pins. That data is
applied to the TDI (trigger data in) pin of U600 and
placed in the Display Logic IC' s internal register to
be read by the Measurement Processor. Both
latches may also be reset via the SIN pin (see
description of A1, AO, and SIN input pins).
B Sweep Logic
The B Sweep logic functions about the same as the
A Sweep logic, except that more signals must be
monitored to determine when the B Sweep can run.
When DM1 and DM0 = 11, the B Sweep can't run at
ARUN: This bit determines whether the A
Sweep is in the free-run mode or in the trig­
gered mode. ARUN=1 selects the free-run
mode.
again goes high.
mode when
That resets the
the sweep is not