Trigger Holdoff, Jitter Counters, And Calibrator - Tektronix 2432 Service Manual

Theory of Operation-2432 Service
Since 0491 is now off, C491 begins the slow-ramp
discharge through 0495 and R493. When the voltage held
on C491 crosses the switching threshold of U490, STOP1
is switched HI to turn off RAMP1 Jitter Correction Counter
at the proper count.
At the time of calibration, the JIT1 GAIN Uitter gain-
ramp 1) value is set to the base of the discharge current
source transistor, 0495, so that the ratio between
charging rate and discharging rate is 2500: 1
(approximately 20 mA from the charging current source to
approximately 8 µA discharge current from 0495). The
slow discharge time of C491 allows the RAMP1 Jitter
Correction Counter to convert the peak amplitude of
RAMP1 (dependent on the time that C491 was allowed to
fast charge) into a count relating trigger-event position to
the sample-clock edge.
After the Jitter Counter has been read, the RAMP,
RAMP, SLRMP1, and SLRMP1 signals will be reset to
their inactive states. This again clamps the summing-node
voltage at zero volts and reapplies the charging current to
the node in preparation for the next trigger event.
RAMP2. As mentioned earlier, the RAMP2 Jitter
Correction circuit is running simultaneously, referenced to
the opposite edge of the sample clock. The RAMP2 Jitter
Correction Counter produces a count defining the trigger
point relative to the opposite edge of the sample clock.
Since both ramps have a possibility of an error in their
slow-ramp starting times (due to metastable switching of
the SLRMP1 and SLRMP2 signals) there will always be a
chance of error present in the trigger-position count. The
count from both ramps is checked, and the value closest
to the nominal midrange count will be used by the System
µP when placing the repetitively sampled data points. If
both counts are in error, that acquisition is discarded.
TRIGGER HOLDOFF, JITTER COUNTERS,
AND CALIBRATOR
Circuitry shown in diagram 13 performs a variety of
functions.
The Trigger Holdoff circuits allow a delay to occur
between the occurrence of a triggering event and when
the A/B Trigger Generator is allowed to recognize another
trigger event. Variable Holdoff can help the user prevent
double triggering on aperiodic signals (such as complex
digital words).
3-58
The RAMP1 and RAMP2 Jitter Correction Counters
measure the time difference between the asynchronous
trigger event and the actual sampling point of the
waveform data. That information is needed by the System
µP to place the random samples taken in REPET acquisi-
tion mode correctly with respect to data points taken in
the previous acquisitions to fill the waveform record.
The Calibrator circuit generates a square-wave output
having precise amplitude and frequency characteristics.
The CALIBRATOR signal provided at the front-panel con-
nector is useful for adjusting probe compensation and veri-
fying VOL TS/DIV and SEC/DIV calibration.
The Side Board Address Decoder included in the cir-
cuitry is used by the System µP to enable the appropriate
register or buffer on the Side board to read the Jitter
Correction Counters, select the Holdoff Time, and com-
municate with the Front Panel µP.
Trigger Holdoff
The Trigger Holdoff circuit consists of a trigger-enabled,
constant current source (actually one of three selectable
sources added to a small permanent source) used to
linearly charge a capacitor (one-of-two selectable cap
values). The resulting integrator output is a linear ramp
whose slope depends on the current-source and
integration-capacitor selection. The ramp is applied to the
Holdoff Comparator where it is compared to the user-
definable (front-panel pot) holdoff-reference level. When the
charging ramp crosses that level, the ramp rapidly
discharges (resets) and ends the holdoff condition.
Holdoff Select
The Holdoff Select circuit, under System µP control,
determines which of the Holdoff Current Sources and
which of the integration capacitors will be used to produce
the holdoff ramp. Its outputs are set by the microproces-
sor by writing data into Holdoff Register U762, residing at
address 620Ch. Output bits HOO through HO2 (holdoff
control bits 0-2) enable their corresponding current-source
transistor when HI. Bit HO3 is used for selection of the
integration capacitor. The FPRESET bit allows the system
processor to reset the Front Panel µP (diagram 3).
Buffer U761, residing at read location 602Ch, allows the
System µP to check the holdoff circuit setup and to moni-
tor the status of the A Trigger (ATG) and trigger holdoff
(A THO) bits.