Display Sequencer Channel Select Logic Bits - Tektronix 2246 1Y Service Manual

Table 3-15

Display Sequencer Channel Select Logic Bits

RD4
RD5 RD3
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
Bit RD2 selects between the A Sweep display and
the B Sweep display (only used in ALT Vertical Mode
(with m easurem ent). The A Sweep is displayed if
this bit is set high (outputs HD1, HDO = 01), other­
wise the B Sweep is displayed
HDO = 1 0 ) . Bit RD1 controls the DS (delay select)
output pin in ALT Vertical Mode (with or without
measurem ent). Finally, bit RDO marks the last state
in a display sequence. When the RDO bit goes high,
the sequencer finishes its current state and jumps
back to the initial state (RAM address 000 is the
initial state). In ALT Vertical Mode, the sequencer
will advance to the next state either on each rising
edge of the trigger holdoff pulse (ALT Vertical Mode
with measurem ent), or on every other rising edge of
the trigger holdoff pulse (ALT Vertical Mode with no
m easurem ent).
The first type of ALT Mode is used when there is an
intensified zone (with or without an accompanying
B Sweep) for only one or two of the displayed
channel (s); every display state can be completely
specified by programming the RAM properly (no
more than eight display states are ever needed for
any measurement display sequence; hence, the
RAM is limited to eight addresses). The second type
of ALT Mode is used when there are intensified
zones and B Sweeps for all channels displayed. In
this mode, HD1 and HDO automatically alternate
between the A sweep and the B Sweep on each
rising edge of the trigger holdoff pulse. Whenever
HD1 and HDO switch from the B Sweep back to the A
Sweep, the vertical sequencer advances to its next
state. This second type of ALT Vertical Mode is used
only when more than eight RAM locations are
needed to define a long display sequence in ALT
Horizontal Mode.
In ALT Vertical Mode, the vertical and horizontal dis­
play enable outputs are initialized as follows: the
trigger holdoff output
processor interface), RESET is strobed, then trigger
holdoff is unforced to allow sweeps to occur. This
procedure ensures that the display enable and trig­
ger source outputs are initialized to the first state of
the programmed display sequence.
Channel
CH 1
CH 2
CH 1 + CH 2
CH 3
CH 4
(outputs HD1,
is forced high (via the
Theory of Operation—2246 1Y and 2246 Mod A Service
In CHOP Vertical Mode, the leading edge of the chop
blanking pulses advance the vertical display enable
outputs. RAM bits RD5, RD4, and RD3 still determine
the vertical channel displayed, and RAM bit RDO
marks the last display state in the sequence. RAM
bits RD2, and RD1 are not used in CHOP Mode.
Other circuitry, clocked by the trigger holdoff pulse,
drives the horizontal display control outputs. The
same initialization procedure as described above for
ALT Vertical Mode is used. However, only the trigger
source and horizontal display enable outputs are
initialized. The vertical-display-enable outputs cycle
at the CHOP rate. Table 3-16 specifies the behavior
of the horizontal- display-enable outputs for all hori­
zontal and vertical modes.
Trigger Holdoff Timer
When the B ENDS A control bit is low, the holdoff
timer is triggered by the rising edge of A GATE.
When the B ENDS A control bit is high, the holdoff
timer is triggered by either the rising edge of
B GATE, or the rising edge of A GATE, whichever
occurs first. The THO output pin will go high
immediately, and go low after the programmed
number of holdoff oscillator cycles. In SGL SEQ
Mode (again, with the TEST input pin high), the
EOSS (end of single sequence) flag will go high and
the THO output will stay high after the last A Sweep
of the programmed sequence. Strobing RESET will
reset the EOSS flag, and set the THO output back
low again, if THO hasn't been forced high via the
Measurement Processor interface.
HOLDOFF OSCILLATOR. A relaxation oscillator circuit
formed by U601, Q600, Q601 and associated com­
ponents is connected between the OSC OUT and
OSC RST pins to provide the input count pulses to
the holdoff timer. The HOLDOFF voltage applied to
the base of Q600 sets up a charging current into
timing capacitor C600. When the holdoff timer is
inactive, the OSC RST output pin is high, and C600 is
held discharged. With the capacitor discharged, the
output of the oscillator is held high. When a rising
edge of A GATE (or B GATE in B ends A mode)
occurs, the OSC RST output will go low and allow the
voltage across C600 to ramp up. When this voltage
crosses an upper threshold, the output of U601 at
pin 7 goes low. This negative transition increments
the internal holdoff counter, and causes the OSC
RST output to go high, again discharging C600.
When the voltage drops below a lower threshold, the
oscillator output again goes high to repeat the oscil­
lation cycle. After the last negative transition on the
OSC OUT pin for a particular count length, the OSC
RST output will go high and stay there until the next
time the THO timer is triggered.
3-23