A And B Sweeps And Delay Comparators (Diagram 5) - Tektronix 2246 1Y Service Manual

Display Logic Clock
The Display Logic clock signal at 10 MHz is generated
by a transistor oscillator circuit composed of Q608,
Y600, and associated components. The frequency of
oscillation is controlled by a ceramic resonator, Y600,
in the feedback path from the collector to the base of
Q608.
A AND B SWEEPS AND DELAY
COMPARATORS (Diagram 5)
Sweep Control Shift Registers
Two serial shift registers provide the control interface
between the Measurement Processor and the A and B
Sweep circuitry. Control bits loaded into registers
U302 for A Sweep and U303 for B Sweep are serially
clocked from the SR DATA line by the SRI CLK pulse.
The states of the loaded bits select the A and B
Sweep timing by choosing the correct charging cur­
rent and timing capacitor to provide the full range of
sweep speeds. Other control bits loaded into the two
registers select the delay voltage applied to the Delay
Comparators and the output voltage from the VOLTS
CAL circuit (used for measurement SELF CAL). Extra
bits are shifted through the two shift registers into the
Auxiliary Data Register (U1103, Diagram 3) via the
AUX DATA signal line to control the trigger bandwidth,
the TV Sync Detector switching, and the functions of
10X MAG, X -Y display, and Vertical Comparator
enabling.
A and B Sweep Timing
Refer to Figure 3 -4 for a simplified schematic of the A
Sweep circuitry.
TIMING RESISTORS. The Sweep Timing resistors in
resistor pack R313 are shared between the A Sweep
and the B Sweep circuitry; those in resistor pack
R321 are divided between the two sweep circuits.
Timing Resistor selection is done by multiplexers
U308 and U307 for the A Sweep and by U310 and
U311 for the B Sweep. The multiplexers are driven by
the Measurement Processor via control bits loaded
into Shift Register 1 (U302 and U303). (See Table
3-22 for the control bit coding.)
SEC/DIV VAR CIRCUIT. Variable sweep speed is con­
trolled by the TIME VAR voltage applied to operational
amplifier U309B. The amplifier controls the current
passing through Darlington transistor Q301 to the
REV OCT 1991
Theory of Operation—2246 1Y and 2246 Mod A Service
voltage divider formed by resistor pack R313. The
voltages at the taps of the voltage divider set the for­
ward bias on the charging-current pass transistor,
Q307, via operational amplifier U304. When the
SEC/DIV VAR control is in its detent (calibrated) posi­
tion, diode CR301 is reverse biased, and the divider
formed by R311 and R314 between the +2.5 V refer­
ence and ground precisely sets the input voltage to
the noninverting input of U309B. With a fixed voltage
output from U309B, the current through Q301 and
R313 is also a fixed value. When the SEC/DIV VAR
control is rotated out of its detent position, the volt­
age at the junction of R309 and R310 decreases to
forward bias CR301. The input voltage to U309B and,
therefore, the current to R313 decreases in propor­
tion to the amount of rotation of the SEC/DIV VAR
control. A decreasing voltage at the output taps of
R313 decreases the charging current through Q307 to
increase the sweep ramp time.
A AND B SWEEP TIMING CAPACITORS. The timing
capacitor selection circuitry is similar for the A and
the B Sweep, but the B Sweep has fewer range steps
and doesn't require two selectable capacitors. Only
the A Sweep timing capacitor selection is described;
like components in the B Sweep circuit do the same
job.
Timing capacitance for the A Sweep is made up of a
combination of fixed, variable, stray, and selectable
components. Sweep timing for the fastest A Sweep
speeds is done with a combination of the fixed,
variable, and stray capacitance and the selectable
charging current supplied through R321, U308, Q307
and Q330. When the slower sweep speeds are
selected, additional capacitors must be switched into
the circuit to produce a longer charging time. The ca­
pacitors that are always in the A Sweep charging path
are C315 (a fixed capacitor), C314 (a variable ca­
pacitor used to adjust the A Sweep timing at the fast­
est sweep speeds),
capacitance.
The base-to-collector junction capacitance Q330
changes as the voltage between the base and collec­
tor of Q330 increases during ramp up. At the fastest
A Sweep speeds, that change would affect the timing
at the start of the charging ramp. To compensate for
the junction-capacity effect of Q330, transistor Q328
(connected as a diode) is added between the charg­
ing current path and the A Sweep Buffer output. The
capacitive current through the reverse-biased junc­
tion of Q328 adds current to the output to make up for
the current required to charge the base-to-collector
capacity of Q330 in the input of the Sweep Buffer.
and the stray circuit
3-31