Cpu Number-Based Data Assurance - Mitsubishi Electric MELSEC iQ-R C R12CCPU-V User Manual

CPU number-based data assurance

Data communication is performed in 64-bit units between CPU modules. Therefore, when data larger than 64 bits are
handled, data inconsistency in which old and new data overlap may occur for each CPU, and this depends on the timing
between data reading by the host CPU and data writing by another CPU/data receiving from other CPU.
Prevention of data inconsistency using the CPU number-based data assurance
The table below shows whether or not to prevent data inconsistency by enabling/disabling the CPU number-based data
assurance.
: With data inconsistency control by system, : Without data inconsistency control by system
*1 The countermeasures by a program are required.
Communication method
*2
Communication by refresh
Communication through direct access
*2 Communication by refresh can not be performed since the CPU buffer memory does not have the refresh area.
*3 The access in the multiple CPU synchronous interrupt program (I45) only.
• CPU No.1 does not send/receive the following data until it receives the notification of the data read
completion from another CPU. The timing of sending/receiving data is the update interval of the CPU
module of which scan time of the programmable controller CPU or refresh cycle of the C Controller module
is the latest.
• C Controller module notifies the contents equivalent to the read completion in each refresh cycle.
• In the data communication through direct access to the CPU buffer memory excluding the fixed cycle
communication area, the data in the CPU buffer memory of another CPU is directly read after the execution
of the read instruction. Therefore, it will not be subject to the CPU number-based data assurance.
• When the data in the CPU buffer memory of a C Controller module is read by a programmable controller
CPU using the refresh, it will not be subject to the CPU number-based data assurance.
CPU buffer memory
CPU number-based CPU number-based
data assurance data assurance
enabled disabled
 
 
*1
Fixed cycle communication area
CPU number-based CPU number-based
data assurance data assurance
enabled disabled
 
*3
 
8 MULTIPLE CPU SYSTEM FUNCTIONS
8.4 Data Communication Between CPU Modules
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