Mitsubishi Electric MELSEC iQ-R C R12CCPU-V User Manual page 166

CPU number-bases data assurance setting
Configure the CPU number-based data assurance setting.
[System Parameter]  [Multiple CPU Setting]  [Communication Setting between CPU]  [PLC Unit Data]
Window
Displayed items
Item
PLC Unit Data
Data assurance by program
Prevent data inconsistency using a program when the data inconsistency control by system is not available.
■Accessing the CPU buffer memory
A program reads data in order from the start address of the CPU buffer memory excluding the refresh area, and writes send
data in order from the end address to the start address excluding the refresh area by the write instruction. Therefore, data
inconsistency can be prevented by setting a device for interlock at the head of data to be communicated.
■Accessing the fixed cycle communication area
When accessing within a multiple CPU synchronous interrupt program (I45), no interlock circuit is required with the CPU
number-based data assurance setting is enabled. To access the fixed cycle communication area in a program other than the
above, or when the CPU number-based data assurance setting is disabled, an interlock circuit is required as with the access
to the CPU buffer memory.
8 MULTIPLE CPU SYSTEM FUNCTIONS
164
8.4 Data Communication Between CPU Modules
Description
Select this to prevent data inconsistency in each CPU
and to send/received data in data communication
between CPU modules by refresh.
Setting range
• Disable (not notify the read
completion to other CPUs)
• Enable (notify the read
completion to other CPUs)
Default
Disable (not notify the read
completion to other CPUs)