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■Prevention of 64-bit data inconsistency
To avoid 64-bit data inconsistency, access the specified start address of the CPU buffer memory in multiples of four similarly
to the device to be specified.
Device
D0
4 words (64 bits)
4 words (64 bits)
D8
4 words (64 bits)
D12
4 words (64 bits)
Checking memory configuration
Memory configuration can be checked with CW Configurator.
[System Parameter] [Multiple CPU Setting] [Communication Setting between CPU] [CPU Buffer Memory
Setting] [<Detailed Setting>]
Window
Displayed items
Item
[Setting] button in each refresh area
[Send/Receive Direction Display between
CPUs] button
8 MULTIPLE CPU SYSTEM FUNCTIONS
154
8.4 Data Communication Between CPU Modules
Data is assured.
Fixed cycle communication area
Data is not assured.
Description
Click the button to configure the refresh settings used for data
communication between CPU modules.
Click the button to display the arrow that indicates the send/receive
direction.
HG1000
HG1004
Address of a multiple of 4
HG1010
Address that is not a multiple of 4
Setting
range
Default
0 points
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