Mitsubishi Electric MELSEC iQ-R C R12CCPU-V User Manual page 165

■Communication through direct access (when C Controller module is on the sending side)
When the CPU number-based data assurance is enabled, the data is not assured.
C Controller module Programmable controller CPU Programmable controller CPU Programmable controller CPU
(CPU No.1) (CPU No.2) (CPU No.3) (CPU No.4)
Fixed cycle Fixed cycle Fixed cycle Fixed cycle
communication communication communication communication
area area area area
Ó Ó
Ó
Without
refresh
function
Ô Ô Ô
Device Device Device Device
Õ
Õ
Ò
Õ
8
CCPU_ToBufHG_ISR( );
The data is written from the program.
At the multiple CPU synchronous interrupt program (I45) execution, the data is read.
At the multiple CPU synchronous interrupt program (I45) execution, the data is refreshed.
The data read completion from each CPU is notified to the CPU No.1.
8 MULTIPLE CPU SYSTEM FUNCTIONS
163
8.4 Data Communication Between CPU Modules