Data Communication Between Cpu Modules - Mitsubishi Electric MELSEC iQ-R C R12CCPU-V User Manual

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8.4

Data Communication Between CPU Modules

Data can be sent/received among CPU modules in a multiple CPU system. The direct access communication enables data
writing or reading among CPU modules.
Communication method
Data communication with CPU buffer
memory
Data communication with fixed cycle
communication area
Used memory
CPU buffer memory is used for data communication among CPU modules.
Memory configuration of CPU buffer memory
CPU buffer memory
Send area of CPU No.1
Send area of CPU No.2
Send area of CPU No.3
Send area of CPU No.4
Area
CPU buffer memory
Fixed cycle communication area
Application
Use this communication method when
performing data send/receive at the
timing of each CPU module.
Use this communication method when
performing data send/receive with
adjusting the timing between CPU
modules.
Communication method
Communication through direct
access
Communication through direct
access
Description
The sending side CPU module writes data to the CPU buffer memory in
the host CPU. The receiving side CPU module reads data from the CPU
buffer memory of the send target CPU module (another CPU).
The sending side CPU module writes data in the fixed cycle
communication area (send area) in the host CPU. The receiving side
CPU module reads data from the fixed cycle communication area
(receive area) in the CPU module of the send source CPU module.
Description
Reads/writes data in the area of the
host CPU or other CPUs.
Performs data communication between
the host CPU area and other CPU
areas in accordance with the set
interval.
8 MULTIPLE CPU SYSTEM FUNCTIONS
8.4 Data Communication Between CPU Modules
Area size
512K words fixed
Can be set within the range of 0 to 24K
words in total. The send area per single
CPU module can be set within the
range of 0 to 12K words. (Page
156 Setting fixed cycle communication
area)
8
153

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