Samsung FLEX-MUXONENAND KFKAGH6Q4M Specifications page 96

Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)
OTP Block Program Operation Flow Chart
Start
Write 'DFS*, FBA' of Flash
Add: F100h DQ=DFS*, FBA
Select DataRAM for DDP
Add: F101h DQ=DBS*
Write 0 to interrupt register
Add: F241h DQ=0000h
Write 'OTP Access' Command
Add: F220h DQ=0065h
Wait for INT register
low to high transition
Add: F241h DQ[15]=INT
Write Data into DataRAM
Add: DP DQ=Data-in
Data Input
Completed?
* DBS, DFS is for DDP
NOTE :
1) FBA(NAND Flash Block Address) could be omitted or any address.
2) 'Write 0 to interrupt register' step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1
3) Data input could be done anywhere between "Start" and "Write Program Command".
4) FBA must be 0000.
5) FSA must be 00 within program operation.
6) BSA must be 1000 and BSC must be 000.
Write 'FBA' of Flash
Add: F100h DQ=FBA
1)
Write 'FPA, FSA' of Flash
Add: F107h DQ=FPA, FSA
Write 'BSA, BSC' of DataRAM
Add: F200h DQ=0800h
2)
Write 0 to interrupt register
Add: F241h DQ=0000h
Write Program command
Automatically
checked
3)
Wait for INT register
low to high transition
Add: F241h DQ[15]=INT
NO
Read Controller
Status Register
Add: F240h DQ[10]=0(Pass)
OTP Programming completed
Do Cold/Warm/Hot
/NAND Flash Core reset
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4)
5)
6)
2)
Add: F220h
DQ=0080h
Automatically
NO
OTP =0?
L
YES
DQ[14]=1(Lock), DQ[10]=1(Error)
Add: F241h DQ[15]=INT
Add: F240h DQ[10]=1(Error)
/NAND Flash Core reset
OTP Exit
FLASH MEMORY
updated
Update Controller
Status Register
Add: F240h
Wait for INT register
low to high transition
Read Controller
Status Register
Do Cold/Warm/Hot
OTP Exit