Samsung FLEX-MUXONENAND KFKAGH6Q4M Specifications page 51

4gb flex-muxonenand m-die flash memory
Table of Contents

Advertisement

Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)
Controller Status Register Output Modes
Mode
Operation Ongoing
Operation OK
Operation Fail
Program fail on Cache Program
Previous program fail during Cache Program
Program fail after Finish Cache Program
Reset during Program/Erase/Load
Program/Erase to the locked block,
Load to the BootRAM
OTP Program Fail(Lock)
OTP Program Fail
NOTE :
1) "1" for PI
Block Lock, "0" for PI
L
L
2) "1" for 1st Block OTP Lock, "0" for 1st Block OTP Unlock.
3) "1" for OTP Block Lock, "0" for OTP Block Unlock.
4) After Finish Cache Program operation, pass/fail status of Current Cache Program and Previous Cache Program will be updated.
2.8.22 Interrupt Status Register F241h (R/W)
This Read/Write register shows status of the Flex-MuxOneNAND interrupts.
F241h, defaults = 8080h after Cold Reset; 8010h after Warm/Hot Reset
15
14
13
12
INT
Reserved(0000000)
Interrupt (INT)
This is the master interrupt bit. The INT bit is wired directly to the INT pin on the chip. Upon writing '0' to the INT bit, the INT pin goes low if
INTpol is high and goes high if INTpol is low.
INT Interrupt [15]
Status
Commands in the command table in page43 (Refer
sets itself to '1'
to Chapter 2.8.18) are completed.
Cold/Warm/Hot reset is being performed, or
clears to '0'
command is written to Command Register in INT
[15]
[14]
[13]
[12]
[11]
OnGo
Reserved
1
0
0
0
0
0000
0
0
0
0
0
Block Unlock.
11
10
9
Conditions
'0' is written to this bit,
auto mode
Controller Status Register [15:0]
[10]
[9]
[8]
[7]
[6]
Reser
Reser
1)
2)
Error
PI
OTP
ved
L
ved
L
0
0/1
0/1
0
0/1
0/1
1
0/1
0/1
1
0/1
0/1
1
0/1
0/1
0
0
1
0/1
0/1
0
0/1
0/1
1
0/1
0/1
1
0/1
1
1
0/1
0
8
7
6
5
RI
WI
EI
Default State
Cold
1
- 51 -
FLASH MEMORY
[5]
[4]
[3]
[2]
[1]
3)
Reserved
Previous
Current
OTPB
L
0/1
0
0
0/1
0
0
0/1
0
0
0/1
0
1
0/1
1
0
00
0/1
(Note 4)
(Note 4)
0/1
0
0
0/1
0
0
1
0
0
0
0
0
4
3
2
1
RSTI
Reserved(0000)
Valid
Interrupt
State
Function
Warm/hot
1
0
0
1
Pending
1
0
[0]
TO
0
0
0
0
0
0
0
0
0
0
0
off
off

Advertisement

Table of Contents
loading

Table of Contents