Samsung FLEX-MUXONENAND KFKAGH6Q4M Specifications page 52

Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)
Read Interrupt (RI)
This is the Read interrupt bit.
RI Interrupt [7]
Status
At the completion of a Load, Superload or LSB Page
sets itself to '1' Recovery Read Operation.
Cold/Warm/Hot reset is being performed, or
clears to '0'
command is written to Command Register in INT auto
Write Interrupt (WI)
This is the Write interrupt bit.
WI Interrupt [6]
Status
At the completion of an Program Operation
sets itself to '1'
Cold/Warm/Hot reset is being performed, or com-
clears to '0'
mand is written to Command Register in INT auto
Erase Interrupt (EI)
This is the Erase interrupt bit.
EI Interrupt [5]
Status
At the completion of an Erase Operation
sets itself to '1'
Cold/Warm/Hot reset is being performed, or com-
clears to '0'
mand is written to Command Register in INT auto
Conditions
(0000h, 0003h or 0005h)
'0' is written to this bit,
mode
Conditions
(0080h and 007Fh)
'0' is written to this bit,
mode
Conditions
(0094h and 0030h)
'0' is written to this bit,
mode
Default State
Cold Warm/hot
1
Default State
Cold Warm/hot
0 0
Default State
Cold Warm/hot
0 0
- 52 -
FLASH MEMORY
Valid Interrupt
State Function
0 0 off
→
0 1 Pending
→
1 0 off
Valid Interrupt
State Function
0 off
→
0 1 Pending
→
1 0 off
Valid Interrupt
State Function
0 off
→
Pending
0 1
→
off
1 0