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Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)
6.15 Cold Reset Timing
POR triggering level
System Power
OneNAND
Operation
RP
INT
INT bit
IOBE bit
INTpol bit
NOTE :
1) Bootcode copy operation starts 400us later than POR activation.
The system power should reach Vcc after POR triggering level(typ. 1.5V) within 400us for valid boot code data.
2) 1KB Bootcode copy and internal update operation take 250us(estimated) from sector0 and 1/page0/block0 of NAND Flash array to BootRAM.
Host can read Bootcode in BootRAM(1K bytes) after Bootcode copy completion.
3) INT register goes 'Low' to 'High' on the condition of 'Bootcode-copy done' and RP rising edge.
If RP goes 'Low' to 'High' before 'Bootcode-copy done', INT register goes to 'Low' to 'High' as soon as 'Bootcode-copy done'
1)
Sleep
0 (default)
1 (default)
- 126 -
Bootcode - copy done
Bootcode copy
2)
High-Z
0 (default)
FLASH MEMORY
Idle
3)
1
1
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