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Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)
Reset Interrupt (RSTI)
This is the Reset interrupt bit.
RSTI Interrupt [4]
Status
At the completion of an Reset Operation
sets itself to '1'
clears to '0'
command is written to Command Register in INT
2.8.23 Start Block Address Register F24Ch (R/W)
This Read/Write register shows the NAND Flash block address in the Write Protection mode. Setting this register precedes a 'Lock Block'
command, 'Unlock Block' command, or 'Lock-Tight' Command.
F24Ch, default = 0000h
15
14
13
12
Reserved(000000)
Device
4Gb
2.8.24 Start Block Address Register F24Dh (R/W)
This register is reserved for future use.
2.8.25 NAND Flash Write Protection Status Register F24Eh (R)
This Read register shows the Write Protection Status of the NAND Flash memory array.
To read the write protection status, FBA(DFS and DBS also in case of DDP) has to be set before reading the register
F24Eh, default = 0002h
15
14
13
12
Write Protection Status Information[2:0]
Item
Bit
US
2
LS
1
LTS
0
Conditions
(00B0h, 00F0h, 00F3h or
warm reset is released)
'0' is written to this bit, or
auto mode
11
10
9
8
Number of Block
1024
11
10
9
8
Reserved(0000000000000)
Definition
Unlocked Status
Locked Status
Locked-Tight Status
- 53 -
Default State
Cold
Warm/hot
0
1
7
6
5
4
SBA
7
6
5
4
Description
1 = current NAND Flash block is unlocked
1 = current NAND Flash block is locked
Or First Block of NAND Flash Array is Locked to be OTP
1 = current NAND Flash block is locked-tight
FLASH MEMORY
Valid
Interrupt
State
Function
0
off
→
0
1
Pending
→
1
0
off
3
2
1
0
SBA
[9:0]
.
3
2
1
0
US
LS
LTS
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