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Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)
5.4 AC Characteristics for Synchronous Burst Read
See Timing Diagrams 6.1 and 6.2
Parameter
Clock
Clock Cycle
Initial Access Time
Burst Access Time Valid Clock to Output Delay
AVD Setup Time to CLK
AVD Hold Time from CLK
AVD High to OE Low
Address Setup Time to CLK
Address Hold Time from CLK
Data Hold Time from Next Clock Cycle
Output Enable to Data
CE Disable to Output & RDY High Z
OE Disable to Output High Z
CE Setup Time to CLK
CLK High or Low Time
2)
CLK
to RDY valid
CLK to RDY Setup Time
RDY Setup Time to CLK
CE low to RDY valid
NOTE :
1) If OE is disabled at the same time or before CE is disabled, the output will go to high-z by t
If CE is disabled at the same time or before OE is disabled, the output will go to high-z by t
If CE and OE are disabled at the same time, the output will go to high-z by t
2) It is the following clock of address fetch clock.
66MHz
Symbol
Min
Max
CLK
1
66
t
15
CLK
t
-
70
IAA
t
-
11
BA
t
5
AVDS
t
2
AVDH
t
0
AVDO
t
5
ACS
t
6
ACH
t
3
BDH
t
-
20
OE
1)
-
20
t
CEZ
1)
-
15
t
OEZ
t
6
CES
t
t
/3
CLKH/L
CLK
t
-
11
RDYO
t
-
11
RDYA
t
4
RDYS
t
-
15
CER
.
OEZ
.
CEZ
.
OEZ
- 111 -
FLASH MEMORY
83MHz
Min
Max
1
83
-
12
-
-
70
-
9
-
4
-
-
2
-
-
0
-
-
4
-
-
6
-
-
2
-
-
20
-
20
-
15
-
4.5
-
-
5
-
-
9
-
9
-
3
-
-
15
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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