Samsung FLEX-MUXONENAND KFKAGH6Q4M Specifications page 130

Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)
6.20 Toggle Bit Timing in Asynchronous Read (VA Transition Before AVD Low)
See AC Characteristics Table 5.5
CE
t
CER
t
OE
OE
t
ASO
WE
t
CA
t
CE
A/DQ0:
1)
VA
A/DQ15
t
AAVDS
AVD
t
AVDP
t
AA
2)
RDY
Note :
NOTE :
1) VA=Valid Read Address, RD=Read Data.
2) Before IOBE is set to 1, RDY and INT pin are High-Z state.
3) Refer to chapter 5.5 for tASO description and value.
6.21 Toggle Bit Timing in Asynchronous Read (VA Transition After AVD Low)
See AC Characteristics Table 5.5
CE
t
CER
OE
t
ASO
t
AVDO
WE
t
CA
A/DQ0:
1)
VA
A/DQ15
t
ACC
t
AAVDS
AVD
t
Hi-Z
2)
RDY
NOTE :
1) VA=Valid Read Address, RD=Read Data.
2) Before IOBE is set to 1, RDY and INT pin are High-Z state.
3) Refer to chapter 5.5 for tASO description and value.
t
RC
t
AVDO
1)
Status RD
t
AAVDH
t
RC
t
OE
t
CE
1)
Status RD
t
AAVDH
AVDP
t
CEZ
t
OEZ
VA
Hi-Z
t
CEZ
t
OEZ
t
CA
VA
Hi-Z
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FLASH MEMORY
Hi-Z
Status RD
Hi-Z
Hi-Z
Status RD