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Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)
3.2 Device Bus Operation
The device bus operations are shown in the table below.
Operation
Standby
Warm Reset
Asynchronous Write
Asynchronous Read
Start Initial Burst Read
Burst Read
Terminate Burst Read
Cycle
Terminate Burst Read
Cycle via RP
Terminate Current Burst
Read Cycle and Start
New Burst Read Cycle
Start Initial Burst Write
Burst Write
Terminate Burst Write
Cycle
Terminate Burst Write
Cycle via RP
Terminate Current Burst
Write Cycle and Start
New Burst Write Cycle
NOTE :
1) L=VIL (Low), H=VIH (High), X=Don't Care.
CE
OE
WE
H
X
X
X
X
X
L
H
L
L
L
H
L
H
H
L
L
H
H
X
H
X
X
X
L
H
H
L
H
L
L
H
X
H
H
X
X
X
X
H
L
- 57 -
FLASH MEMORY
ADQ0~15
RP
High-Z
H
High-Z
L
Add. In /Data
H
In
Add. In /Data
H
Out
Add. In
H
Burst Data
H
Out
High-Z
H
High-Z
L
Add In
H
Add In
H
Data In
H
High-Z
H
High-Z
L
Add In
H
CLK
AVD
X
X
X
X
L
L
H
X
X
X
X
H
X
X
X
X
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