External Port - Analog Devices ADSP-21161N EZ-KIT Lite Manual

The ADSP-21161N processor's core voltage is 1.8V, the external (IO)
interface voltage is 3.3V.
A 25 MHz through-hole oscillator supplies the input clock to the proces-
sor. Footprints are provided on the board for a surface-mount oscillator
and a through-hole crystal for alternate user-installed clocks. The speed at
which the core operates is determined by the location of the clock mode
switch ( ) as described in
SW10
page 2-5 and Table
Table 2-1. ADSP-21161N EZ-KIT Lite Clock Modes
CLKDBL CLK_CFG1
OFF ON
OFF ON
OFF OFF
ON ON
ON ON
ON OFF

External Port

The external port (EP) of the processor connects to a 512K x 8-bit flash
memory. The flash memory connects to the boot memory select (
pin and the memory select 1 (
memory to be used to boot the processor as well as to store information
during normal operation.
The external memory interface also connects to 48 MB (8M x 48 bit)
SDRAM memory. The SDRAM memory connects to the memory select 0
( ) pin. Refer to
~MS0
ADSP-21161N EZ-KIT Lite Evaluation System Manual
www.BDTIC.com/ADI
ADSP-21161N EZ-KIT Lite Hardware Reference
"Clock Mode Selection Switch (SW10)" on
2-1. By default, the processor core runs at 100 MHz.
CLK_CFG0
ON
OFF
ON
ON
OFF
ON
) pin. The connection allows the flash
~MS1
"SDRAM Disable Jumper (P17)" on page 2-8
Core Clock Ratio EP Clock Ratio
2:1 1X
3:1 1X
4:1 1X (default)
4:1 2X
6:1 2X
8:1 2X
)
~BMS
for
2-3