External Port - Analog Devices ADSP-21375 Manual

The pin of the processor connects to a 16.384 MHz oscillator. The
CLKIN
core frequency of the processor is derived by multiplying the frequency at
the pin by a value determined by the state of the processor pins
CLKIN
and
CLKCFG1 CLKCFG0
the switch (see
SW2
page 2-10). By default, the EZ-KIT Lite gives a core frequency of
262.144 MHz. It is possible to change the speed of the processor by
changing the value of the
The switch also configures the boot mode of the processor. The
SW2
EZ-KIT Lite is capable of EPROM/flash boot and SPI boot. By default,
the EZ-KIT Lite boots from the flash memory. For information about
configuring the boot modes, see
Switch (SW2)" on page

External Port

The external port of the ADSP-21375 processor consists of a 24-bit
address bus, 16-bit data memory bus, and control lines. The control lines
are used to select, read, and write to external memory devices.
The external port connects to an 8-bit parallel flash memory and a 16-bit
SDRAM memory. See
tion about accessing the flash and SDRAM memories.
All of the external port signals are available externally via the expansion
interface connectors (
"ADSP-21375 EZ-KIT Lite Schematic" on page
ADSP-21375 EZ-KIT Lite Evaluation System Manual
ADSP-21375 EZ-KIT Lite Hardware Reference
. The value at these pins is determined by the state of
"Boot Mode and Clock Ratio Select Switch (SW2)" on
register.
PMCTL
"Boot Mode and Clock Ratio Select
2-10.
"External Memory" on page 1-7
). The pinout of the connectors can be found in
J1–3
for more informa-
B-1.
2-3