Anybus CompactCom 40 Network Manual page 135

Appendix G: Backward Compatibility
G.3.5 Control Register CTRL_AUX-bit
30-series
40-series
All released Anybus CompactCom 30 example drivers from HMS comply with this difference.
Related Information: Anybus CompactCom 40 Software Design Guide (HMSI-216-125), section
"Control Register".
G.3.6 Status Register STAT_AUX-bit
30-series
40-series
All released Anybus CompactCom 30 example drivers from HMS comply with this difference.
Related Information: Anybus CompactCom 40 Software Design Guide (HMSI-216-125), section
"Status Register".
G.3.7 Control Register CTRL_R-bit
30-series
40-series
All released CompactCom 30 example drivers from HMS comply with this difference.
Related Information: Anybus CompactCom 40 Software Design Guide (HMSI-216-125), section
"Control Register".
G.3.8 Modifications of Status Register, Process Data Read Area, and
Message Data Read Area
In the 40-series, the Status Register, the Process Data Read Area, and the Message Data Read
Area are write protected in hardware (parallel interface). If the software for some reason writes
to any of those areas, a change is needed.
All released Anybus CompactCom 30 example drivers from HMS comply with this difference.
Anybus CompactCom 40 EtherNet/IP Transparent Ethernet Network Guide
The CTRL_AUX bit in the control register indicates to the Anybus CompactCom if the
process data in the current telegram has changed compared to the previous one.
The value of the CTRL_AUX bit is always ignored. Process data is always accepted.
The STAT_AUX bit in the status register indicates if the output process data in the current
telegram has changed compared to the previous one. This functionality must be enabled
in the Anybus object (01h), Attribute #15. By default, the STAT_AUX bit functionality is
disabled.
The STAT_AUX bit indicates updated output process data (not necessarily changed data)
from the network compared to the previous telegram. The functionality is always enabled.
The application may change this bit at any time.
For the 8-bit parallel operating mode, the bit is only allowed to transition from 1 to 0 when
the STAT_M-bit is set in the status register. When using the serial operating modes, it is
also allowed to transition from 1 to 0 in the telegram immediately after the finalizing empty
fragment.
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SCM-1202-019-EN 1.6