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80960MC
Table 4. 80960MC Pin Description: L-Bus Signals (Sheet 2 of 3)
NAME
TYPE
ADS
O
O.D.
W/R
O
O.D.
DT/R
O
O.D.
DEN
O
O.D.
READY
I
LOCK
I/O
O.D.
BE3:0
O
O.D.
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
10
ADDRESS/DATA STATUS indicates an address state. ADS is asserted every T
state and deasserted during the following T
asserted again every T
state where READY was asserted in the previous cycle.
d
WRITE/READ specifies, during a T
It is latched on-chip and remains valid during T
DATA TRANSMIT / RECEIVE indicates the direction of data transfer to and from
the L-Bus. It is low during T
it is high during T
and T
a
d
is asserted.
DATA ENABLE (active low) enables data transceivers. The processor asserts
DEN# during all T
and T
d
w
80960MC.
READY indicates that data on LAD lines can be sampled or removed. When
READY is not asserted during a T
by inserting a wait state (T
BUS LOCK prevents bus masters from gaining control of the L-Bus during
Read/Modify/Write (RMW) cycles. The processor or any bus agent may assert
LOCK.
At the start of a RMW operation, the processor examines the LOCK pin. When the
pin is already asserted, the processor waits until it is not asserted. When the pin is
not asserted, the processor asserts LOCK during the T
action. The processor deasserts LOCK in the T
During the time LOCK is asserted, a bus agent can perform a normal read or write
but not a RMW operation.
The processor also asserts LOCK during interrupt-acknowledge transactions.
Do not leave LOCK unconnected. It must be pulled high for the processor to
function properly.
BYTE ENABLE LINES specify the data bytes (up to four) on the bus which are
used in the current bus cycle. BE3 corresponds to LAD31:24; BE0 corresponds to
LAD7:0.
The byte enables are provided in advance of data:
Byte enables asserted during T
Byte enables asserted during T
word to be transmitted following the next assertion of READY).
Byte enables that occur during T
are undefined. Byte enables are latched on-chip and remain constant from one T
cycle to the next when READY is not asserted.
For reads, byte enables specify the byte(s) that the processor actually uses. L-Bus
agents are required to assert only adjacent byte enables (e.g., asserting just BE0
and BE2 is not permitted) and are required to assert at least one byte enable.
Address bits A
and A
can be decoded externally from the byte enables.
0
1
DESCRIPTION
state. For a burst transaction, ADS is
d
cycle, whether the operation is a write or read.
a
cycles.
d
and T
cycles for a read or interrupt acknowledgment;
a
d
cycles for a write. DT/R never changes state when DEN
states. The DEN# line is an open drain-output of the
cycle, the T
cycle is extended to the next cycle
d
d
) and ADS is not asserted in the next cycle.
w
cycle of the write transaction.
a
specify the bytes of the first data word.
a
specify the bytes of the next data word, if any (the
d
cycles that precede the last assertion of READY
d
a
cycle of the read trans-
a
d
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