ABB REG650 Technical Manual page 114

Section 6
Differential protection
108
all phases with set start signal are free of their respective block signals, a
restrained trip TRIPRES and common trip TRIP are issued
3. If a start signal is issued in a phase, and the fault has been classified as internal,
then any eventual block signals are overridden and a unrestrained negative-
sequence trip TRNSUNR and common trip TRIP are issued without any further
delay. This feature is called the unrestrained negative-sequence protection 110%
bias.
4. The sensitive negative sequence differential protection is independent of any start
signals. It is meant to detect smaller internal faults such as turn-to-turn faults,
which are often not detected by the traditional differential protection. The
sensitive negative sequence differential protection starts whenever both
contributions to the total negative sequence differential current (that must be
compared by the internal/external fault discriminator) are higher than the value of
the setting IMinNegSeq. If a fault is positively recognized as internal, and the
condition is stable with no interruption for at least one fundamental frequency
cycle the sensitive negative sequence differential protection TRNSSENS and
common trip TRIP are issued. This feature is called the sensitive negative
sequence differential protection.
5. If a start signal is issued in a phase (see signal STL1), even if the fault has been
classified as an external fault, the instantaneous differential current of that phase
(see signal IDL1) is analyzed for the 2
less harmonic pollution. than allowed by the settings I2/I1Ratio, and I5/I1Ratio it
is assumed that a minor simultaneous internal fault must have occurred. Only
under these conditions a trip command is allowed (the signal TRIPRESL1 is = 1).
The cross-block logic scheme is automatically applied under such circumstances.
(This means that the cross block signals from the other two phases L2 and L3 is
not activated to obtain a trip on the TRIPRESL1 output signal in figure 38)
6. All start and blocking conditions are available as phase segregated as well as
common signals.
IDL1 MAG
a
a>b
I Diff Alarm
b
IDL2 MAG
a
a>b
I Diff Alarm
b
IDL3 MAG
a
a>b
I Diff Alarm
b
IEC06000546 V1 EN
Figure 42: Differential current alarm logic
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and the 5 harmonic contents. If there is
tAlarm Delay
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1MRK 502 048-UEN A
IDALARM
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