Table 7-23 Reset Isolation Register Field Descriptions; Figure 7-16 Reset Isolation Register (Rsiso) - Texas Instruments TMS320C6670 Data Manual

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Table 7-22 Reset Configuration Register Field Descriptions (Part 2 of 2)
Bit Field Description
11-4 Reserved Reserved
3 WDTYPE3 Watchdog timer [N] initiates a reset of type:
0 = Hard reset (default)
2 WDTYPE2
1 = Soft reset
1 WDTYPE1
0 WDTYPE0
End of Table 7-22
7.5.2.9 Reset Isolation Register (RSISO)
This register is used to select the module clocks that must maintain their clocking without pausing through non
power-on reset. Setting any of these bits effectively blocks reset to all PLLCTL Registers in order to maintain current
values of PLL multiplier, divide ratios and other settings. Along with setting module specific bit in RSISO, the
corresponding MDCTLx[12] bit also needs to be set in the PSC to reset-isolate a particular module. For more
information on the MDCTLx Register see the Power Sleep Controller (PSC) for KeyStone Devices User Guide in
2.9 ''Related Documentation from Texas Instruments'' on page
shown in Figure 7-16 and described in
Figure 7-16 Reset Isolation Register (RSISO)
31
Reserved
R-0x0000
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 7-23 Reset Isolation Register Field Descriptions
Bit Field Description
31-10 Reserved Reserved.
9 SRIOISO Isolate SRIO module control
0 = Not reset isolated
1 = Reset isolated
8 SRISO Isolate SmartReflex control
0 = Not reset isolated
1 = Reset isolated
7-4 Reserved Reserved
3 AIF2ISO Isolate AIF2 module control
0 = Not reset isolated
1 = Reset isolated
2-0 Reserved Reserved
End of Table 7-23
Copyright 2012 Texas Instruments Incorporated
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Multicore Fixed and Floating-Point System-on-Chip
Table 7-23.
16 15 10
Reserved
R-0x00
TMS320C6670 Peripheral Information and Electrical Specifications
66. The Reset Isolation register (RSTCTRL) is
9 8 7
SRIOISO SRISO Reserved
R/W-0 R/W-0 R-0x0
TMS320C6670
SPRS689D—March 2012
4 3 2 0
AIF2ISO Reserved
R/W-0
R-000
137