Table of Contents
Advertisement
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689D—March 2012
7.9.5 External Interrupts Electrical Data/Timing
Table 7-47
NMI and LRESET Timing Requirements
(see
Figure
7-30)
No.
1
tsu(LRESET-LRESETNMIENL)
1
tsu(NMI-LRESETNMIENL)
1
tsu(CORESELn-LRESETNMIENL)
2
th(LRESETNMIENL-LRESET)
2
th(LRESETNMIENL-NMI)
2
th(LRESETNMIENL-CORESELn)
3
tw(LRESETNMIEN)
End of Table 7-47
1 P = 1/SYSCLK1 clock frequency in ns.
Figure 7-30
NMI and LRESET Timing
CORESEL[3:0]/
LRESET
/
NMI
LRESETNMIEN
178
TMS320C6670 Peripheral Information and Electrical Specifications
(1)
Setup time - LRESET valid before LRESETNMIEN low
Setup time - NMI valid before LRESETNMIEN low
Setup time - CORESEL[2:0] valid before LRESETNMIEN low
Hold time - LRESET valid after LRESETNMIEN high
Hold time - NMI valid after LRESETNMIEN high
Hold time - CORESEL[2:0] valid after LRESETNMIEN high
Pulsewidth - LRESETNMIEN low width
1
2
3
Copyright 2012 Texas Instruments Incorporated
Submit Documentation Feedback
www.ti.com
Min
Max
Unit
12*P
ns
12*P
ns
12*P
ns
12*P
ns
12*P
ns
12*P
ns
12*P
ns
Advertisement
Table of Contents
