Device Status (Devstat) Register - Texas Instruments TMS320C6670 Data Manual

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Table 3-2 Device State Control Registers (Part 4 of 4)
Address Start Address End
0x02620374 0x02620377
0x02620378 0x0262037B
0x0262037C 0x0262037F
0x02620380 0x02620383
0x02620384 0x02620387
0x02620388 0x026203AF
0x026203B0 0x026203B3
0x026203B4 0x026203B7
0x026203B8 0x026203BB
0x026203BC 0x026203BF
0x026203C0 0x026203C3
0x026203C4 0x026203C7
0x026203C8 0x026203CB
0x026203CC 0x026203CF
0x026203D0 0x026203D3
0x026203D4 0x026203D7
0x026203D8 0x026203DB
0x026203DC 0x026203F7
0x026203F8 0x026203FB
0x026203FC 0x026203FF
0x02620400 0x02620403
0x02620404 0x02620467
End of Table 3-2

3.3.1 Device Status (DEVSTAT) Register

The Device Status Register depicts the device configuration selected upon a power-on reset by either the POR or
RESETFULL pin. Once set, these bits will remain set until a power-on reset. The Device Status Register is shown in
Figure 3-1 and described in
Figure 3-1 Device Status Register
31
Reserved
R-0
Legend: R = Read only; RW = Read/Write; -n = value after reset
1 x indicates the bootstrap value latched via the external pin
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Size Acronym
4B SRIO_SERDES_CFGRX2
4B SRIO_SERDES_CFGTX2
4B SRIO_SERDES_CFGRX3
4B SRIO_SERDES_CFGTX3
4B Reserved
28B Reserved
4B Reserved
4B HYPERLINK_SERDES_CFGPLL
4B HYPERLINK_SERDES_CFGRX0
4B HYPERLINK_SERDES_CFGTX0
4B HYPERLINK_SERDES_CFGRX1
4B HYPERLINK_SERDES_CFGTX1
4B HYPERLINK_SERDES_CFGRX2
4B HYPERLINK_SERDES_CFGTX2
4B HYPERLINK_SERDES_CFGRX3
4B HYPERLINK_SERDES_CFGTX3
4B Reserved
28B Reserved
4B DEVSPEED
4B Reserved
4B PKTDMA_PRI_ALLOC
100B Reserved
Table 3-3.
18 17
PACLKSEL PCIESSEN
Multicore Fixed and Floating-Point System-on-Chip
Description
See ''Related Documentation from Texas Instruments''
See ''Related Documentation from Texas Instruments''
See section 3.3.19
See section 4.4
16 15 14
PCIESSMODE[1:0
R-x R/W-xx
TMS320C6670
SPRS689D—March 2012
''Bus Priorities'' on page 97
13 1
BOOTMODE[12:0]
R/W-xxxxxxxxxxxx
Device Configuration
on page 66
on page 66
0
LENDIAN
(1)
R-x
71