Ipc Acknowledgement Host (Ipcarh) Register; Timer Input Selection Register (Tinpsel); Table 3-15 Ipc Generation Registers Field Descriptions; Table 3-16 Ipc Acknowledgement Register Field Descriptions - Texas Instruments TMS320C6670 Data Manual

TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689D—March 2012
Table 3-15 IPC Generation Registers Field Descriptions
Bit Field Description
31-4 SRCSx Reads return current value of internal register bit.
Writes:
0 = No effect
1 = Sets both SRCSx and the corresponding SRCCx.
3-1 Reserved Reserved
0 IPCG Reads return 0.
Writes:
0 = No effect
1 = Creates an interrupt pulse on device pin (host interrupt/event output in HOUT pin)
End of Table 3-15

3.3.15 IPC Acknowledgement Host (IPCARH) Register

IPCARH registers are provided to facilitate host CPU interrupt. Operation and use of IPCARH is the same as
other IPCAR registers. The IPC Acknowledgement Host Register is shown in
Table 3-16.
Figure 3-14 IPC Acknowledgement Register (IPCARH)
31 30 29
SRCC27 SRCC26 SRCC25
RW +0 RW +0 RW +0
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 3-16 IPC Acknowledgement Register Field Descriptions
Bit Field Description
31-4 SRCCx Reads return current value of internal register bit.
Writes:
0 = No effect
1 = Clears both SRCCx and the corresponding SRCSx
3-0 Reserved Reserved
End of Table 3-16

3.3.16 Timer Input Selection Register (TINPSEL)

Timer input selection is handled within the control register TINPSEL. The Timer Input Selection Register is shown
in Figure 3-15 and described in
Figure 3-15 Timer Input Selection Register (TINPSEL)
31 16
Reserved
0
8 7
TINPLSEL4 TINPHSEL3
RW, +0 RW, +1
Legend: R = Read only; RW = Read/Write; -n = value after reset
80 Device Configuration
28 27
SRCC24 SRCC23 – SRCC4
RW +0 RW +0 (per bit field)
Table 3-17.
15 14
TINPHSEL7 TINPLSEL7
RW, +1 RW, +0
6 5
TINPLSEL3 TINPHSEL2
RW, +0 RW, +1
Figure 3-14
8 7 6
SRCC3 SRCC2 SRCC1
RW +0 RW +0 RW +0
13 12
TINPHSEL6 TINPLSEL6
RW, +1 RW, +0
spacer
4 3
TINPLSEL2 TINPHSEL1
RW, +0 RW, +1
Copyright 2012 Texas Instruments Incorporated
and described in
5 4 3
SRCC0 Reserved
RW +0 R, +0000
11 10
TINPHSEL5 TINPLSEL5
RW, +1 RW, +0
2 1
TINPLSEL1 TINPHSEL0
RW, +1 RW, +1
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0
9
TINPHSEL4
RW, +1
0
TINPLSEL0
RW, +0