Table 7-20 Reset Type Status Register Field Descriptions; Figure 7-13 Reset Type Status Register (Rstype) - Texas Instruments TMS320C6670 Data Manual

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7.5.2.6 Reset Type Status Register (RSTYPE)
The Reset Type Status (RSTYPE) Register latches the cause of the last reset. If multiple reset sources occur
simultaneously, this register latches the highest priority reset source. The Reset Type Status Register is shown in
Figure 7-13 and described in
Figure 7-13 Reset Type Status Register (RSTYPE)
31 29 28
Reserved EMU-RST
R-0 R-0
Legend: R = Read only; -n = value after reset
Table 7-20 Reset Type Status Register Field Descriptions
Bit Field Description
31-29 Reserved Reserved. Read only. Always reads as 0. Writes have no effect.
28 EMU-RST Reset initiated by emulation
0 = Not the last reset to occur
1 = The last reset to occur
27-12 Reserved Reserved. Read only. Always reads as 0. Writes have no effect.
11 WDRST3 Reset initiated by Watchdog Timer[N]
0 = Not the last reset to occur
10 WDRST2
1 = The last reset to occur
9 WDRST1
8 WDRST0
7-3 Reserved Reserved. Read only. Always reads as 0. Writes have no effect.
2 PLLCTLRST Reset initiated by PLLCTL
0 = Not the last reset to occur
1 = The last reset to occur
1 RESET RESET reset
0 = RESET was not the last reset to occur
1 = RESET was the last reset to occur
0 POR Power-on reset
0 = Power-on reset was not the last reset to occur
1 = Power-on reset was the last reset to occur
End of Table 7-20
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Table 7-20.
27 12 11
Reserved
R-0
Multicore Fixed and Floating-Point System-on-Chip
8 7
WDRST[N] Reserved
R-0 R-0
TMS320C6670 Peripheral Information and Electrical Specifications
TMS320C6670
SPRS689D—March 2012
3 2 1
PLLCTRLRST RESET
R-0 R-0
0
POR
R-0
135