IDT 89HPES64H16G2 User Manual page 86

IDT Switch Partitions
Notes
PES64H16G2 User Manual
Changing the operating mode of a port is subject to the requirements and restrictions listed in the sub-
sections below. Since an operating mode change may take a significant amount of time to complete, status
bits are provided to indicate when the change has started and when it has completed.
– The Operating Mode Change Initiated (OMCI) bit in the Switch Port Status (SWPORTxSTS)
register is set when a mode change begins.
– The Operating Mode Change Completed (OMCC) bit in the Switch Port Status (SWPORTxSTS)
register is set when a mode change completes.
The port operating mode change requirements and restrictions differ based on the method used to
program the SWPORTxCTL register.
Port Operating Mode Change Latency
The latency to complete a port operating mode change is set to 2 ms if the port's OMA field is set to 'no
action'. If the port's OMA field is set to 'reset', the latency is 2.5 ms.
Port Operating Mode Change via EEPROM Loading
When modifying the state of a port via the serial EEPROM, it is not possible to check the OMCI and
OMCC bits in the SWPORTxSTS register to obtain an indication of port operating mode change initiation
and completion. As a result, the following requirements and restrictions apply. Violating these requirements
results in undefined behavior.
Prior to modifying the operating mode of a port using EEPROM, it is required that the following proprie-
tary timer registers be set to 0x0. This will ensure instantaneous execution of the port operating mode
change action which in turn facilitates following the rules stated above. The last instructions in the EEPROM
must set these timers back to their default values.
– Side Effect Delay Timer (SEDELAY register)
– Port Operating Mode Change Drain Delay Timer (POMCDELAY register)
– Reset Drain Delay Timer (RDRAINDELAY register)
– Upstream Secondary Bus Reset Delay (USSBRDELAY register)
Modifying the operating mode of a port via serial EEPROM loading requires that the OMA field be set to
'no action'. The following port operating mode changes are allowed. All other port operating mode changes
are not allowed via serial EEPROM.
Unattached  Upstream switch port
Unattached  Downstream switch port
Unattached  Disabled
Changing the operating mode of a port from unattached to upstream switch port mode requires that the
PCI Express capabilities list and PCI Express extended capabilities list in the port's PCI-to-PCI bridge func-
tion be configured via the EEPROM to match the functionality of an upstream port (see section Capability
Structures on page 15-3 for details).
Specifically, the following register fields must be set appropriately.
– NXTPTR field in the PCI Power Management Capabilities (PMCAP) register
– NXTPTR field in the PCI Express VC Extended Capability Header (PCIEVCCAP) register
Refer to section Static Reconfiguration on page 6-15 for a sample partition and port configuration
sequence programmed via the serial EEPROM.
Port Operating Mode Change via Other Methods
When modifying the operating mode of a port via methods other than EEPROM loading (i.e., via PCI
Express configuration requests or using the SMBus slave), the following requirements and restrictions
apply:
– Once an operating mode change to a port has been initiated, this operating mode change must
be allowed to complete (e.g., by polling the OMCC field) before a new operating mode change is
initiated on the same port, or a partition state change is initiated on the partition associated with
the port.
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