IDT 89HPEB383 Manuals

IDT 89HPEB383 Manuals

Manuals and User Guides for IDT 89HPEB383. We have 1 IDT 89HPEB383 manual available for free PDF download: User Manual

IDT 89HPEB383 User Manual

IDT 89HPEB383 User Manual (264 pages)

PCI Express Bridge

Brand: IDT | Category: PCI Card | Size: 3.49 MB

Table of Contents

Table of Contents
3
About this Document

15
- Scope
  15
- Document Conventions
  15
- Revision History
  17
1 Functional Overview

19
- Overview
  19
- Features
  20
  - General Features
    20
  - Figure 1: PEB383 Block Diagram
    20
  - Pcie Features
    21
  - PCI Features
    21
- Device Architecture
  22
- Figure 2: PEB383 Device Architecture
  22
- Typical Applications
  24
- Figure 3: Network Interface Card Application
  24
- Figure 4: DVR Card Application
  25
- Figure 5: Motherboard Application
  25
- Figure 6: Expresscard Application
  26
2 Signal Descriptions

27
- Overview
  27
- Table 1: Pin Types
  27
- Pcie Interface Signals
  28
- Table 2: Pcie Interface Signals
  28
- PCI Interface Signals
  29
- Table 3: PCI Interface Signals
  29
- EEPROM Interface Signals
  32
- Table 4: EEPROM Interface Signals
  32
- JTAG Interface Signals
  33
- Power-Up Signals
  33
- Table 5: JTAG Interface Signals
  33
- Table 6: Power-Up Signals
  33
- Power Supply Signals
  34
- Table 7: Power Supply Signals
  34
3 Data Path

35
- Overview
  35
- Transaction Management
  37
- Buffer Structure
  38
- Flow Control
  40
- Prefetching Algorithm
  41
- Table 9: Initial Credit Advertisement
  41
- Short Term Caching
  42
- Polarity Inversion
  42
4 Addressing

43
- Overview
  43
- Memory-Mapped I/O Space
  43
- Figure 9: Memory-Mapped I/O Address Space
  44
- Prefetchable Space
  45
- I/O Space
  46
- Figure 10: 64-Bit Prefetchable Memory Address Range
  46
- VGA Addressing
  48
- Figure 11: I/O Address Space
  48
- ISA Addressing
  49
- Figure 12: ISA Mode I/O Addressing
  50
- Non-Transparent Addressing
  51
- Legacy Mode
  55
5 Configuration Transactions

57
6 Bridging

63
- Overview
  63
- Flow Control Advertisements
  63
- Buffer Size and Management
  64
- Assignment of Requestor ID and Tag
  64
- Forwarding of Pcie to PCI
  64
  - Pcie Memory Write Request
    64
  - Pcie Non-Posted Requests
    64
- Forwarding of PCI to Pcie
  65
  - PCI Memory Write Request
    65
  - PCI Non-Posted Requests
    66
- PCI Transaction Support
  67
- Table 10: PCI Transaction Support
  67
- Pcie Transaction Support
  68
- Table 11: Pcie Transaction Support
  68
- Message Transactions
  69
  - Intx Interrupt Signaling
    69
  - Power Management
    69
  - Locked Transaction
    69
  - Slot Power Limit
    69
  - Vendor-Defined and Device ID
    69
- Transaction Ordering
  70
- Table 12: Transaction Ordering
  70
- Exclusive Access
  71
7 PCI Arbitration

73
8 Interrupt Handling

77
- Overview
  77
- Figure 21: Interrupt Handling Diagram
  77
- Interrupt Sources
  78
- Interrupt Routing
  78
9 Error Handling

79
10 Reset and Clocking

101
- Reset
  101
  - Table 25: Reset Summary
    101
  - Figure 25: Reset Timing
    102
  - Pcie Link Reset
    102
  - Table 26: Reset Timing
    102
  - PCI Bus Reset
    103
- Clocking
  104
  - Pcie Clocking
    104
  - Figure 26: Pcie Clocking
    104
  - PCI Clocking
    105
  - Figure 27: PCI Clocking
    105
  - Table 27: PCI Clocking
    105
11 Power Management

107
- Overview
  107
  - Features
    107
  - Unsupported Features
    108
- Power Management Capabilities
  108
- Power States
  108
  - Aspm
    108
  - L0 State
    109
  - L0S State
    109
  - L1 State
    109
  - L2/L3 Ready
    109
  - L3 State
    109
  - Ldn State
    109
  - Link State Summary
    110
  - Figure 28: Pcie Link Power Management States
    110
  - Table 28: Pcie Link States
    110
  - Device Power States
    111
  - D0 State
    111
  - D3 Hot State
    111
  - D3 Cold State
    111
  - D State Transitions
    112
  - Power Management Event
    112
  - Figure 29: D State Transitions
    112
  - Power State Summary
    113
  - Table 29: Power Management State Summary
    113
- Power Saving Modes
  114
- Table 30: Power Saving Modes
  114
12 Serial EEPROM

115
- Overview
  115
- System Diagram
  116
- Figure 30: EEPROM Interface
  116
- EEPROM Image
  118
- Table 31: EEPROM Image
  118
- Functional Timing
  119
- Figure 31: 9-Bit EEPROM Read Timing
  119
- Figure 32: 16-Bit EEPROM Read Timing
  120
- Figure 33: 9-Bit EEPROM Write Timing
  120
- Figure 34: 16-Bit EEPROM Write Timing
  121
- Figure 35: EEPROM WREN Instruction Timing
  121
- Figure 36: EEPROM RDSR Instruction Timing
  121
13 Jtag

123
- Overview
  123
- TAP Controller Initialization
  124
- Instruction Register
  124
- Bypass Register
  124
- JTAG Device ID Register
  124
- JTAG Register Access
  125
- Dedicated Test Pins
  127
- Accessing Serdes TAP Controller
  127
- Figure 39: Pcie Serdes Connections
  127
14 Register Descriptions

129
15 Electrical Characteristics

233
16 Packaging

249
- Pinouts and Mechanical Diagrams
  250
  - QFP Package Pinout
    250
  - QFP Package Drawing
    251
  - QFN Package Pinout
    253
  - QFN Package Drawing
    254
- Thermal Characteristics
  256
- Table 52: Thermal Specifications - 66Mhz
  256
- Table 53: Thermal Specifications - 33Mhz
  257
- Moisture Sensitivity
  258
17 Ordering Information

259
Glossary

261
Index

263

Advertisement

Advertisement

Related Products

IDT Categories

Switch

Switch Computer Hardware Microcontrollers Accessories

More IDT Manuals