IDT 89HPES64H16G2 User Manual page 84

IDT Switch Partitions
Notes
PES64H16G2 User Manual
All input signals associated with the port, except the SerDes, are ignored and have no effect on the
operation of the device.
– Boot configuration vector signals are sampled during a switch fundamental reset and thus their
dynamic state has no effect on the operating mode of the port in any port mode.
– The state of the following port signals is ignored: HPxAPN, HPxMRLN, HPxPDN, HPxPFN, and
HPxPWRGDN.
– Since a port in this state is not associated with a switch partition, the state of no switch partition
input signal (e.g., PARTxPERSTN) has effect on the port.
Since the port is not associated with a switch partition in this state, the port is unaffected by the state of
any switch partition, and vice-versa. The port responds to received TLPs as follows.
– The port responds to all received PCI configuration requests that do not target the Global Address
Space Access Address or Data (GASAADDR or GASADATA) registers with a configuration
request retry status completion.
– The port responds to received PCI configuration requests that target the GASAADDR and GASA-
DATA normally (i.e., the requested action is performed and completion generated).
– The port responds to all other received requests by treading them as unsupported requests (i.e.,
logging error status and if appropriate, generating a completion). The port responds to comple-
tions by discarding the completion and returning flow control credits.
– The port responds to all completions as unexpected completions.
All registers associated with the port remain accessible from the global address space.
– All configuration registers in the port are accessible through the global address space by the serial
EEPROM, other ports, and the SMBus.
– Although the link in this mode behaves as an upstream port, all registers in the port's PCI-to-PCI
bridge function take on the organization and initial values shown in Table 15.4 for a downstream
port.
– Registers and fields that affect the behavior of the link (listed below) operate normally (i.e., control
fields control behavior and status fields report status) as though the port were an upstream port.
• PCIELCTL (all fields related to link/phy)
• PCIELSTS (all fields related to link/phy)
• PCIELCTL2 (all fields related to link/phy)
• PCIELSTS2 (all fields related to link/phy)
• SERDESCFG
• LANESTS[1:0]
• PHYPRBS
Registers other than those listed above operate as though the port were a downstream port and take on
the initial value of a downstream port. A port in this mode is unaffected by the following.
– The reception of TS1 ordered-sets indicating a hot reset.
– The data link layer of the port transitions to the DL_Down state.
– The reception of a Set_Slot_Power_Limit message.
Since the link operates as an upstream port, an automatic speed change is not initiated when the link
enters L0. Automatic speed change may be enabled by modifying the value of the Initial Link Speed
Change Control (ILSCC) bit in the Phy Link Configuration 0 (PHYLCFG0) register.
Upstream Switch Port
A port in upstream switch port mode behaves as the upstream port of a switch partition.
– All output signals associated with a downstream port are placed in a negated state (i.e., hot-plug
signals). The negated value of HPxAIN, HPxILOCKP, HPxPEP, HPxPIN, and HPxRSTN is deter-
mined as shown in Table 10.2.
The PCI-to-PCI bridge associated with the upstream port has an associated type 1 header. The device
and function number are zero.
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