IDT 89HPES64H16G2 User Manual page 73

IDT Reset and Initialization
Notes
PES64H16G2 User Manual
The operation of a switch fundamental reset with serial EEPROM initialization is illustrated in Figure 5.1.
Stable Stable
Power
GCLK
GCLK*
> 100ns
Vdd
PERSTN
SerDes
Master SMBus
Slave SMBus
1. Clock not shown to scale
Figure 5.1 Switch Fundamental Reset with Serial EEPROM Initialization
The operation of a switch fundamental reset using RSTHALT is illustrated in Figure 5.2.
Stable
Stable
Power
GCLK
GCLK*
Vdd
> 100ns
PERSTN
SerDes
RSTHALT
Slave SMBus
1. Clock not shown to scale
Figure 5.2 Fundamental Reset Using RSTHALT to Keep Device in Quasi-Reset State
< 100 ms
~285 s ~2 s
PLL Reset & Lock
CDR Lock
< 200 ms
Switch Ports held in Quasi-Reset Mode
< 100 ms
~285 s ~2 s
PLL Reset & Lock
CDR Lock Link Training
Boot Vector sampled and RSTHALT bit in SWCTL register is set
Switch Ports held in Quasi-Reset Mode
5 - 5
Link Ready
Link Training
Serial EEPROM Initialization
Ready
Ready for Normal Operation
Switch ports begin to process TLPs normally
Link Ready
Ready for Normal Operation
RSTHALT bit in SWCTL cleared (e.g., via slave SMBus)
Switch ports begin to process TLPs normally
April 5, 2013