IDT 89HPES64H16G2 User Manual page 72

IDT Reset and Initialization
Notes
PES64H16G2 User Manual
9. Within 100 ms following clearing of the switch fundamental reset condition, the following occurs.
– All ports that have PCI Express base specification compliant link partners have completed link
training.
– All ports are able to receive and process TLPs.
10. If the sampled Switch Mode (SWMODE[3:0]) state corresponds to a mode that supports serial
EEPROM initialization, then the contents of the serial EEPROM are read and appropriate switch
registers are updated.
– While the contents of the EEPROM are read, the switch responds to all configuration request with
configuration-request-retry-status completion.
– If a one is written by the serial EEPROM to the Full Link Retrain (FLRET) bit in any Phy Link State
0 (PHYLSTATE0) register, then link retraining is initiated on the corresponding port using the
current link parameters.
– If an error is detected during loading of the serial EEPROM, then loading of the serial EEPROM
is aborted and the RSTHALT bit is set in the SWCTL register. Error information is recorded in the
SMBUSSTS register.
– When serial EEPROM initialization completes, the EEPROM Done (EEPROMDONE) bit in the
SMBUSSTS register is set and the switch ports start processing configuration requests normally,
unless the RSTHALT bit in the SWCTL register is set.
If serial EEPROM initialization completes with an error, the RSTHALT bit in the SWCTL register
is set as described in section Initialization from Serial EEPROM on page 13-2. In this case, the
ports enter a quasi-reset state as described in step 11.
11. If the RSTHALT bit in the SWCTL register is set (e.g., due to the assertion of the RSTHALT signal in
the sampled boot vector), the ports enter a quasi-reset state.
– In quasi-reset state, the port responds to all type 0 configuration request TLPs with a configura-
tion-request-retry-status completion
returned but the TLP is discarded).
– The ports remain in quasi-reset state until the Reset Halt (RSTHALT) bit is cleared by software in
the SWCTL register.
This provides a synchronization point for a device on the slave SMBus to initialize the device.
When device initialization is completed, the slave SMBus device clears the RSTHALT bit allow-
ing the device to begin normal operation.
12. The Register Unlock (REGUNLOCK) bit is cleared in the Switch Control (SWCTL) register.
13. Normal device operation begins as dictated by the SWMODE value in the boot configuration vector.
The PCI Express 2.0 specification indicates that a device must respond to Configuration Request trans-
actions within 100ms from the end of Conventional Reset (cold, warm, or hot). Additionally, the PCI Express
specification indicates that a device must respond to Configuration Requests with a Successful Completion
within 1.0 second after Conventional Reset of a device. The reset sequence above guarantees that the
switch will be ready to respond successfully to configuration requests within the 1.0 second period as long
as the serial EEPROM initialization process completes within 200 ms.
– Under normal circumstances, 200 ms is more than adequate to initialize registers in the device
even with a Master SMBus operating frequency of 100 KHz.
Serial EEPROM initialization may cause writes to register fields that initiate side effects such as link
retraining. These side effects are initiated at the point at which the write occurs. Therefore, serial EEPROM
initialization should be structured in a manner so as to ensure proper configuration prior to initiation of these
side effects.
1.
This includes configuration requests to the Global Address Space Access and Data registers (GASAADDR and
GASADATA). Type 1 configuration request TLPs are handled as unsupported requests.
1
. All other TLPs are ignored (i.e., flow control credits are
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