IDT 89HPES64H16G2 User Manual page 250

IDT PCI to PCI Bridge and Proprietary Port Specific Registers
AERCTL - AER Control (0x118)
Bit
Field
4:0
5
6
7
8
9
10
31:11
AERHL1DW - AER Header Log 1st Doubleword (0x11C)
Bit
Field
31:0
AERHL2DW - AER Header Log 2nd Doubleword (0x120)
Bit
Field
31:0
AERHL3DW - AER Header Log 3rd Doubleword (0x124)
Bit
Field
31:0
PES64H16G2 User Manual
Field Default
Type
Name Value
FEPTR RO 0x0
Sticky
ECRCGC RWL 0x1
ECRCGE RW 0x0
Sticky
ECRCCC RWL 0x1
ECRCCE RW 0x0
Sticky
MHRC RO 0x0
MHRE RO 0x0
Sticky
Reserved RO 0x0
Field Default
Type
Name Value
HL RWL 0x0
Sticky
Field Default
Type
Name Value
HL RWL 0x0
Sticky
Field Default
Type
Name Value
HL RWL 0x0
Sticky
Description
First Error Pointer. This field contains a pointer to the bit in the
AERUES register that resulted in the first reported error. This field
is valid only when the bit in the AERUES register pointed to by this
field is set.
ECRC Generation Capable. This bit indicates if the Function is
capable of generating ECRC.
ECRC Generation Enable. When this bit is set, ECRC generation
is enabled for the Function.
ECRC Check Capable. This bit indicates if the Function is capable
of checking ECRC.
ECRC Check Enable. When this bit is set, ECRC checking is
enabled for the Function.
Multiple Header Recording Capable. The PES64H16G2 ports do
not support recording of multiple packet headers.
Multiple Header Recording Enable. The PES64H16G2 ports do
not support recording of multiple packet headers. As a result, this
bit is hardwired to 0x0.
Reserved field.
Description
Header Log. This field contains the 1st doubleword of the TLP
header that resulted in the first reported uncorrectable error.
Description
Header Log. This field contains the 2nd doubleword of the TLP
header that resulted in the first reported uncorrectable error.
Description
Header Log. This field contains the 3rd doubleword of the TLP
header that resulted in the first reported uncorrectable error.
16 - 40 April 5, 2013