IDT 89HPES64H16G2 User Manual page 249

IDT PCI to PCI Bridge and Proprietary Port Specific Registers
Bit Field
Field Name
7 BADDLLP
8 RPLYROVR
11:9 Reserved
12 RPLYTO
13 ADVISORYNF
14
15
31:16 Reserved
PES64H16G2 User Manual
Default
Type
Value
RW 0x0
Sticky
RW 0x0
Sticky
RO 0x0
RW 0x0
Sticky
RW 0x1
Sticky
CIE RW 0x1
Sticky
HLO RW 0x1
Sticky
RO 0x0
Description
Bad DLLP Mask. When this bit is set, the corresponding bit in the
AERCES register is masked. When a bit is masked in the AERCES
register, the corresponding event is not reported to the root com-
plex.
This bit does not affect the state of the corresponding bit in the
AERCES register.
Replay Number Rollover Mask. When this bit is set, the corre-
sponding bit in the AERCES register is masked. When a bit is
masked in the AERCES register, the corresponding event is not
reported to the root complex.
This bit does not affect the state of the corresponding bit in the
AERCES register.
Reserved field.
Replay Timer Timeout Mask. When this bit is set, the corre-
sponding bit in the AERCES register is masked. When a bit is
masked in the AERCES register, the corresponding event is not
reported to the root complex.
This bit does not affect the state of the corresponding bit in the
AERCES register.
Advisory Non-Fatal Error Mask. When this bit is set, the corre-
sponding bit in the AERCES register is masked. When a bit is
masked in the AERCES register, the corresponding event is not
reported to the root complex.
This bit does not affect the state of the corresponding bit in the
AERCES register.
Correctable Internal Error Mask. When this bit is set, the corre-
sponding bit in the AERCES register is masked. When a bit is
masked in the AERCES register, the corresponding event is not
reported to the root complex.
This bit does not affect the state of the corresponding bit in the
AERCES register.
When the Internal Error Reporting Enable (IERROREN) bit is
cleared in the Internal Error Reporting Control (IERRORCTL) reg-
ister, this field becomes read-only with a value of zero.
Header Log Overflow Mask. When this bit is set, the correspond-
ing bit in the AERCES register is masked. When a bit is masked in
the AERCES register, the corresponding event is not reported to
the root complex.
This bit does not affect the state of the corresponding bit in the
AERCES register.
When the Internal Error Reporting Enable (IERROREN) bit is
cleared in the Internal Error Reporting Control (IERRORCTL) reg-
ister, this field becomes read-only with a value of zero.
Reserved field.
16 - 39 April 5, 2013