IDT 89HPES64H16G2 User Manual page 248

IDT PCI to PCI Bridge and Proprietary Port Specific Registers
Bit
Field
6
7
8 RPLYROVR
11:9
12
13 ADVISORYNF
14
15
31:16
AERCEM - AER Correctable Error Mask (0x114)
Bit
Field
0
5:1
6
PES64H16G2 User Manual
Field Default
Type
Name Value
BADTLP RW1C 0x0
Sticky
BADDLLP RW1C 0x0
Sticky
RW1C 0x0
Sticky
Reserved RO 0x0
RPLYTO RW1C 0x0
Sticky
RW1C 0x0
Sticky
CIE RW1C 0x0
Sticky
HLO RW1C 0x0
Sticky
Reserved RO 0x0
Field Default
Type
Name Value
RCVERR RW 0x0
Sticky
Reserved RO 0x0
BADTLP RW 0x0
Sticky
Description
Bad TLP Status. This bit is set when a bad TLP is detected.
Bad DLLP Status. This bit is set when a bad DLLP is detected.
Replay Number Rollover Status. This bit is set when a replay
number rollover has occurred indicating that the data link layer has
abandoned replays and has requested that the link be retrained.
Reserved field.
Replay Timer Timeout Status. This bit is set when the replay
timer in the data link layer times out.
Advisory Non-Fatal Error Status. This bit is set when an advisory
non-fatal error is detected as described in Section 6.2.3.2.4 of the
PCI Express 2.0 specification.
Correctable Internal Error Status. This bit is set whenever an
correctable internal error associated with the port is detected.
Header Log Overflow Status. This bit is set when an error that
requires packet-header logging occurs but the packet header can-
not be logged by the port's AER Header Log registers
(AERHL[1:4]DW).
A packet's header cannot be logged in the AER Header Log regis-
ters when an error occurs while the First Error Pointer (FEPTR field
in the AERCTL register) is valid. The First Error Pointer is valid
when it points to a set bit in the AERUES register (i.e., indicating
the occurrence of a prior uncorrectable error which has not been
cleared by software).
Reserved field.
Description
Receiver Error Mask. When this bit is set, the corresponding bit in
the AERCES register is masked. When a bit is masked in the
AERCES register, the corresponding event is not reported to the
root complex.
This bit does not affect the state of the corresponding bit in the
AERCES register.
Reserved field.
Bad TLP Mask. When this bit is set, the corresponding bit in the
AERCES register is masked. When a bit is masked in the AERCES
register, the corresponding event is not reported to the root com-
plex.
This bit does not affect the state of the corresponding bit in the
AERCES register.
16 - 38 April 5, 2013