IDT 89HPES64H16G2 User Manual page 247

IDT PCI to PCI Bridge and Proprietary Port Specific Registers
Bit
Field
14
15
16
17
18 MALFORMED
19
20
21
22
23
31:24
AERCES - AER Correctable Error Status (0x110)
Bit
Field
0
5:1
PES64H16G2 User Manual
Field Default
Type
Name Value
COMPTO RO
CABORT RO
UECOMP RW
Sticky
RCVOVR RW
Sticky
RW
Sticky
ECRC RW
Sticky
UR RW
Sticky
ACSV RW
Sticky
UIE RW
Sticky
MCBLKTLP RW
Sticky
Reserved RO
Field Default
Type
Name Value
RCVERR RW1C
Sticky
Reserved RO
0x0 Completion Timeout Severity. A switch port does not initiate non-
posted requests on its own behalf. Therefore, this field is hardwired
to zero.
0x0 Completer Abort Severity. Tthe switch never responds to a non-
posted request with a completer abort, except for ACS violations.
0x0 Unexpected Completion Severity. This bit controls the severity
of the reported error. If this bit is set, the event is reported as a fatal
error. When this bit is cleared, the event is reported as a non-fatal
error.
0x1 Receiver Overflow Severity. This bit controls the severity of the
reported error. If this bit is set, the event is reported as a fatal error.
When this bit is cleared, the event is reported as a non-fatal error.
0x1 Malformed TLP Severity. This bit controls the severity of the
reported error. If this bit is set, the event is reported as a fatal error.
When this bit is cleared, the event is reported as a non-fatal error.
0x0 ECRC Severity. This bit controls the severity of the reported error.
If this bit is set, the event is reported as a fatal error. When this bit
is cleared, the event is reported as a non-fatal error.
0x0 UR Severity. This bit controls the severity of the reported error. If
this bit is set, the event is reported as a fatal error. When this bit is
cleared, the event is reported as a non-fatal error.
0x0 ACS Violation Severity. This bit controls the severity of the
reported error. If this bit is set, the event is reported as a fatal error.
When this bit is cleared, the event is reported as a non-fatal error.
0x1 Uncorrectable Internal Error Severity. This bit controls the
severity of the reported error. If this bit is set, the event is reported
as a fatal error. When this bit is cleared, the event is reported as a
non-fatal error.
When the Internal Error Reporting Enable (IERROREN) bit is
cleared in the Internal Error Reporting Control (IERRORCTL) reg-
ister, this field becomes read-only with a value of one.
0x0 MC Blocked TLP Severity. This bit controls the severity of the
reported error. If this bit is set, the event is reported as a fatal error.
When this bit is cleared, the event is reported as a non-fatal error.
When the Disable Multicast Error Reporting (DMCER) bit is
cleared in the Switch Control (SWCTL) register, this field becomes
read-only with a value of zero.
0x0 Reserved field.
0x0 Receiver Error Status. This bit is set when the physical layer
detects a receiver error.
0x0 Reserved field.
16 - 37
Description
Description
April 5, 2013