IDT PCI to PCI Bridge and Proprietary Port Specific Registers
Bit
Field
22
23
31:24
AERUESV - AER Uncorrectable Error Severity (0x10C)
Bit
Field
0
3:1
4
5
SDOENERR
11:6
12
13
PES64H16G2 User Manual
Field
Default
Type
Name
Value
UIE
RW
Sticky
MCBLKTLP
RW
Sticky
Reserved
RO
Field
Default
Type
Name
Value
UDEF
RW
Sticky
Reserved
RO
DLPERR
RW
Sticky
RW
Sticky
Reserved
RO
POISONED
RW
Sticky
FCPERR
RW
Sticky
0x1
Uncorrectable Internal Error Mask. When this bit is set, the cor-
responding bit in the AERUES register is masked. When a bit is
masked in the AERUES register, the corresponding event is not
logged in the advanced capability structure, the First Error Pointer
field (FEPTR) in the AERCTL register is not updated, and an error
is not reported to the root complex.
This bit does not affect the state of the corresponding bit in the
AERUES register.
When the Internal Error Reporting Enable (IERROREN) bit is
cleared in the Internal Error Reporting Control (IERRORCTL) reg-
ister, this field becomes read-only with a value of zero.
0x0
MC Blocked TLP Mask. When this bit is set, the corresponding bit
in the AERUES register is masked. When a bit is masked in the
AERUES register, the corresponding event is not logged in the
advanced capability structure, the First Error Pointer field (FEPTR)
in the AERCTL register is not updated, and an error is not reported
to the root complex.
This bit does not affect the state of the corresponding bit in the
AERUES register.
When the Disable Multicast Error Reporting (DMCER) bit is set in
the Switch Control (SWCTL) register, this field becomes read-only
with a value of zero.
0x0
Reserved field.
0x0
Undefined. This bit is no longer used in this version of the specifi-
cation.
0x0
Reserved field.
0x1
Data Link Protocol Error Severity. This bit controls the severity
of the reported error. If this bit is set, the event is reported as a fatal
error. When this bit is cleared, the event is reported as a non-fatal
error.
0x1
Surprise Down Error Severity. This bit controls the severity of the
reported error. If this bit is set, the event is reported as a fatal error.
When this bit is cleared, the event is reported as a non-fatal error.
0x0
Reserved field.
0x0
Poisoned TLP Status Severity. This bit controls the severity of
the reported error. If this bit is set, the event is reported as a fatal
error. When this bit is cleared, the event is reported as a non-fatal
error.
0x1
Flow Control Protocol Error Severity. This bit controls the sever-
ity of the reported error. If this bit is set, the event is reported as a
fatal error. When this bit is cleared, the event is reported as a non-
fatal error.
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Description
Description
April 5, 2013
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